Pin

Name

Description

8

TXMOD

The transmitter RF output voltage is proportional to the input current to this pin. A series resistor is used to adjust

the peak transmitter output voltage. 0 dBm output power requires about 250 µA of input current. In the ASK mode,

minimum output power occurs when the modulation driver sinks about 10 µA of current from this pin. In the OOK

mode, input signals less than 220 mV completely turn the transmitter oscillator off. Internally, this pin appears to

mately:

A ±5% resistor value is recommended. In the OOK mode, this pin is usually driven with a logic-level data input

(unshaped data pulses). OOK modulation is practical for data pulses of 30 µs or longer. In the ASK mode, this pin

accepts analog modulation (shaped or unshaped data pulses). ASK modulation is practical for data pulses 8.7 µs

or longer. The resistor driving this pin must be low in the receive and power-down (sleep) modes. Please refer to

the ASH Transceiver Designer’s Guide for additional information on modulation techniques.

9

LPFADJ

4.5 kHz to 1.8 MHz. The resistor value is determined by:

equiripple phase response. The peak drive current available from RXDATA increases in proportion to the filter

bandwidth setting.

10

GND2

GND2 is an IC ground pin. It should be connected to GND1 by a short, low inductance trace.

11

RREF

RREF is the external reference resistor pin. A 100 K reference resistor is connected between this pin and ground.

A ±1% resistor tolerance is recommended. It is important to keep the total capacitance between ground, Vcc and

this node to less than 5 pF to maintain current source stability. If THLD1 and/or THDL2 are connected to RREF

through resistor values less that 1.5 K, their node capacitance must be added to the RREF node capacitance and

the total should not exceed 5 pF.

12

THLD2

THLD2 is the “dB-below-peak” data slicer (DS2) threshold adjust pin. The threshold is set by a 0 to 200 K resistor

tector value (increases difference) from 0 to 120 mV. For most applications, this threshold should be set at 6 dB

below peak, or 60 mV for a 50%-50% RF amplifier duty cycle. The value of the THLD2 resistor is given by:

A ±1% resistor tolerance is recommended for the THLD2 resistor. Leaving the THLD2 pin open disables the

dB-below-peak data slicer operation.

13

THLD1

old is increased by increasing the resistor value. Connecting this pin directly to RREF provides zero threshold.

The value of the resistor depends on whether THLD2 is used. For the case that THLD2 is not used, the accept-

able range for the resistor is 0 to 100 K, providing a THLD1 range of 0 to 90 mV. The resistor value is given by:

For the case that THLD2 is used, the acceptable range for the THLD1 resistor is 0 to 200 K, again providing a

THLD1 range of 0 to 90 mV. The resistor value is given by:

A ±1% resistor tolerance is recommended for the THLD1 resistor. Note that a non-zero DS1 threshold is required

for proper AGC operation.

14

PRATE

The interval between the falling edge of an ON pulse to the first RF amplifier and the rising edge of the next ON

A ±5% resistor value is recommended. When the PWIDTH pin is connected to Vcc through a 1 M resistor, the RF

amplifiers operate at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the period

A ±5% resistor value should also be used in this case. Please refer to the ASH Transceiver Designer’s Guide for

additional amplifier duty cycle information. It is important to keep the total capacitance between ground, Vcc and

this pin to less than 5 pF to maintain stability.

10