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CLC730036 Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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CLC730036 Datasheet(HTML) 1 Page - National Semiconductor (TI) |
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1 / 6 page  The CLC730038 and CLC730036 evaluation boards are designed to aid in the characterization of Comlinear’s 8-pin, dual monolithic amplifiers. s CLC730038 - DIP packages Uses all through-hole components s CLC730036 - SOIC packages Uses all surface-mount components Both boards have identical circuit configurations and are designed for non-inverting gains. Inverting gains or other circuit configurations can be obtained with slight modifications to the boards. Use the evaluation boards as a: s Guide for high frequency layout s Tool to aid in device testing and characterization Basic Operation Figure 1 shows the non-inverting schematic for both boards. The input signal is brought into the board through SMA connectors to the non-inverting input of the amplifier. The resistor Rin is used to set the input termination resistance to the op amp. The non- inverting gain is set by the following equation: Non-inverting Gain: The value of the feedback resistor, Rf, has a strong influence on AC performance. Refer to the product data sheet for feedback resistor selection. The output of the op amp travels through a series resistance, Rout, and then leaves the board through an SMA connector. The series resistance, Rout, matches transmission lines or isolates the output from capacitive loads. Figure 1: Non-inverting Gain Configurations Inverting Gain Operation The evaluation boards can be modified to provide an inverting gain configuration. Complete these steps to modify the board: 1. Cut the input trace as shown in Figure 2 2. Use 25 Ω for R in 3. Terminate Rg at the input trace instead of ground (See Figure 2) 4. Add Rt for desired input impedance (input impedance = Rg||Rt) Figure 2: Modifications for Inverting Gains (CLC730038 board shown) Figure 3 illustrates the inverting schematic for both boards. Figure 3: Inverting Gain Configurations Isolation and Channel Matching Performance For maximum isolation between channels, proper power supply decoupling is required. Always include the bypass capacitors C1, C2, C3, and C4. The use of good quality capacitors also helps to achieve better isolation performance. The evaluation boards have also been designed to mini- mize channel-to-channel crosstalk. The input and output pins of the amplifier are sensitive to the coupling of par- asitic capacitances caused by power or ground planes and traces. To reduce the influence of these parasitics, the ground plane has been removed around these sen- sitive nodes. In multilayer boards, remove both the ground and power traces and planes around the input and output pins. 8-Pin Dual Op Amp Eval. Boards Part Numbers CLC730038, CLC730036 September 1997 + - Channel 1 Rf1 C1 C3 OUT1 IN1 +VCC C2 C4 -VCC 3 2 4 8 1 + + Rg1 Rin1 Rout1 + - Channel 2 Rf2 Rg2 Rin2 5 6 7 Rout2 OUT2 IN2 730038 REVC RF1 RG1 RIN1 IN1 Rt 25 Ω Cut Here + - Channel 1 Rf1 C1 C3 OUT1 IN1 +VCC C2 C4 -VCC 3 2 4 8 1 + + Rt1 25 Ω Rin1 Rout1 Rg1 Select Rt to yield desired input impedance = Rg||Rt Rg2 + - Channel 2 Rf2 OUT2 IN2 5 6 7 Rt2 25 Ω Rin2 Rout2 1 R R f g + © 1997 National Semiconductor Corporation http://www.national.com Printed in the U.S.A. N |
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