V

+

GRT

12

10,11

13

8

+IN

V

±

7

INPUT ZEROING

SWITCH

GAIN RESISTORS

SCK

SDI

SDO

CS

DGND

5

3

4

2

6

POWER DOWN

INPUT ZERO

FREQ. COMP.

GAIN DECODE

LATCH

SHIFT REGISTER

X16

X1

-

+

V

-

SCK

SDI

SDO

CS

DGND

5

3

4

7

2

6

GRT

+IN

INPUT

ZEROING

8

12

10,11

13

GAIN

SET

V

+

FREQ.

COMP.

SERIAL CONTROL

INTERFACE

POWER

DOWN

+

-

LMP8100

SNOSAO1B – JULY 2007 – REVISED APRIL 2008

www.ti.com

Simplified Block Diagram

Block Diagram

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

2

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