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MCIMX6S5EVM10AB Datasheet(PDF) 95 Page - Freescale Semiconductor, Inc |
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MCIMX6S5EVM10AB Datasheet(HTML) 95 Page - Freescale Semiconductor, Inc |
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95 / 168 page  Electrical Characteristics i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor 95 4.11.9 I2C Module Timing Parameters This section describes the timing parameters of the I2C module. Figure 64 depicts the timing of I2C module, and Table 67 lists the I2C module timing characteristics. Figure 64. I2C Bus Timing Table 67. I2C Module Timing Parameters ID Parameter Standard Mode Fast Mode Unit Min Max Min Max IC1 I2Cx_SCL cycle time 10 — 2.5 — µs IC2 Hold time (repeated) START condition 4.0 — 0.6 — µs IC3 Set-up time for STOP condition 4.0 — 0.6 — µs IC4 Data hold time 01 1 A device must internally provide a hold time of at least 300 ns for I2Cx_SDA signal to bridge the undefined region of the falling edge of I2Cx_SCL. 3.452 2 The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2Cx_SCL signal. 01 0.92 µs IC5 HIGH Period of I2Cx_SCL Clock 4.0 — 0.6 — µs IC6 LOW Period of the I2Cx_SCL Clock 4.7 — 1.3 — µs IC7 Set-up time for a repeated START condition 4.7 — 0.6 — µs IC8 Data set-up time 250 — 1003 3 A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC7) of 250 ns must be met. This automatically is the case if the device does not stretch the LOW period of the I2Cx_SCL signal. If such a device does stretch the LOW period of the I2Cx_SCL signal, it must output the next data bit to the I2Cx_SDA line max_rise_time (IC9) + data_setup_time (IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the I2Cx_SCL line is released. —ns IC9 Bus free time between a STOP and START condition 4.7 — 1.3 — µs IC10 Rise time of both I2Cx_SDA and I2Cx_SCL signals — 1000 20 + 0.1Cb 4 4 C b = total capacitance of one bus line in pF. 300 ns IC11 Fall time of both I2Cx_SDA and I2Cx_SCL signals — 300 20 + 0.1Cb 4 300 ns IC12 Capacitive load for each bus line (Cb) — 400 — 400 pF IC10 IC11 IC9 IC2 IC8 IC4 IC7 IC3 IC6 IC10 IC5 IC11 START STOP START START I2Cx_SDA I2Cx_SCL IC1 |
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