MCIMX6S5DVM10AC datasheet(86/168 Pages) FREESCALE

Part #	MCIMX6S5DVM10AC

Description	Applications Processors for Consumer Products

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Manufacturer	FREESCALE [Freescale Semiconductor, Inc]

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i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 3

86

Freescale Semiconductor

Electrical Characteristics

1 ENET_RX_EN, ENET_RX_CLK, and ENET0_RXD0 have the same timing in 10 Mbps 7-wire interface mode.

4.11.5.1.2

MII Transmit Signal Timing (ENET_TX_DATA3,2,1,0, ENET_TX_EN,

ENET_TX_ER, and ENET_TX_CLK)

The transmitter functions correctly up to an ENET_TX_CLK maximum frequency of 25 MHz + 1%.

There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed

twice the ENET_TX_CLK frequency.

Figure 49 shows MII transmit signal timings. Table 60 describes the timing parameters (M5–M8) shown

in the figure.

Figure 49. MII Transmit Signal Timing Diagram

1 ENET_TX_EN, ENET_TX_CLK, and ENET0_TXD0 have the same timing in 10-Mbps 7-wire interface mode.

4.11.5.1.3

MII Asynchronous Inputs Signal Timing (ENET_CRS and ENET_COL)

Figure 50 shows MII asynchronous input timings. Table 61 describes the timing parameter (M9) shown in

the figure.

Figure 50. MII Async Inputs Timing Diagram

Table 60. MII Transmit Signal Timing

ID

Characteristic1

Min.

Max.

Unit

M5

ENET_TX_CLK to ENET_TX_DATA3,2,1,0, ENET_TX_EN,

ENET_TX_ER invalid

5—

ns

M6

ENET_TX_CLK to ENET_TX_DATA3,2,1,0, ENET_TX_EN,

ENET_TX_ER valid

—20

ns

M7

ENET_TX_CLK pulse width high

35%

65%

ENET_TX_CLK period

M8

ENET_TX_CLK pulse width low

35%

65%

ENET_TX_CLK period

ENET_TX_CLK (input)

ENET_TX_DATA3,2,1,0

M7

M8

M5

M6

ENET_TX_ER

ENET_TX_EN

(outputs)

ENET_CRS, ENET_COL

M9

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