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MCIMX6S8DVM10AC Datasheet(PDF) 99 Page - Freescale Semiconductor, Inc |
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MCIMX6S8DVM10AC Datasheet(HTML) 99 Page - Freescale Semiconductor, Inc |
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99 / 168 page  Electrical Characteristics i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor 99 4.11.10.3 Electrical Characteristics Figure 67 depicts the sensor interface timing. IPUx_CSIx_PIX_CLK signal described here is not generated by the IPU. Table 69 lists the sensor interface timing characteristics. Figure 67. Sensor Interface Timing Diagram 4.11.10.4 IPU Display Interface Signal Mapping The IPU supports a number of display output video formats. Table 70 defines the mapping of the Display Interface Pins used during various supported video interface formats. Table 69. Sensor Interface Timing Characteristics ID Parameter Symbol Min Max Unit IP1 Sensor output (pixel) clock frequency Fpck 0.01 180 MHz IP2 Data and control setup time Tsu 2 — ns IP3 Data and control holdup time Thd 1 — ns Table 70. Video Signal Cross-Reference i.MX 6Solo/6DualLite LCD Comment1,2 Port Name (x=0, 1) RGB, Signal Name (General) RGB/TV Signal Allocation (Example) 16-bit RGB 18-bit RGB 24 Bit RGB 8-bit YCrCb3 16-bit YCrCb 20-bit YCrCb IPUx_DISPx_DAT00 DAT[0] B[0] B[0] B[0] Y/C[0] C[0] C[0] — IPUx_DISPx_DAT01 DAT[1] B[1] B[1] B[1] Y/C[1] C[1] C[1] — IPUx_DISPx_DAT02 DAT[2] B[2] B[2] B[2] Y/C[2] C[2] C[2] — IPUx_DISPx_DAT03 DAT[3] B[3] B[3] B[3] Y/C[3] C[3] C[3] — IPUx_DISPx_DAT04 DAT[4] B[4] B[4] B[4] Y/C[4] C[4] C[4] — IPUx_DISPx_DAT05 DAT[5] G[0] B[5] B[5] Y/C[5] C[5] C[5] — IPUx_DISPx_DAT06 DAT[6] G[1] G[0] B[6] Y/C[6] C[6] C[6] — IP3 IPUx_CSIx_DATA_EN, IPUx_CSIx_VSYNC, IP2 1/IP1 IPUx_CSIx_PIX_CLK (Sensor Output) IPUx_CSIx_HSYNC |
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