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MCIMX6S8DVM10AC Datasheet(PDF) 85 Page - Freescale Semiconductor, Inc |
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MCIMX6S8DVM10AC Datasheet(HTML) 85 Page - Freescale Semiconductor, Inc |
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85 / 168 page  Electrical Characteristics i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor 85 4.11.4.4 Bus Operation Condition for 3.3 V and 1.8 V Signaling 4.11.5 Signaling level of SD/eMMC4.3 and eMMC4.4/4.41 modes is 3.3 V. Signaling level of SDR104/SDR50 mode is 1.8 V. The DC parameters for the NVCC_SD1, NVCC_SD2 and NVCC_SD3 supplies are identical to those shown in Table 24, "GPIO DC Parameters," on page 40.Ethernet Controller (ENET) AC Electrical Specifications The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. 4.11.5.1 ENET MII Mode Timing This subsection describes MII receive, transmit, asynchronous inputs, and serial management signal timings. 4.11.5.1.1 MII Receive Signal Timing (ENET_RX_DATA3,2,1,0, ENET_RX_EN, ENET_RX_ER, and ENET_RX_CLK) The receiver functions correctly up to an ENET_RX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the ENET_RX_CLK frequency. Figure 48 shows MII receive signal timings. Table 59 describes the timing parameters (M1–M4) shown in the figure. Figure 48. MII Receive Signal Timing Diagram Table 59. MII Receive Signal Timing ID Characteristic1 Min. Max. Unit M1 ENET_RX_DATA3,2,1,0, ENET_RX_EN, ENET_RX_ER to ENET_RX_CLK setup 5— ns M2 ENET_RX_CLK to ENET_RX_DATA3,2,1,0, ENET_RX_EN, ENET_RX_ER hold 5— ns M3 ENET_RX_CLK pulse width high 35% 65% ENET_RX_CLK period M4 ENET_RX_CLK pulse width low 35% 65% ENET_RX_CLK period ENET_RX_CLK (input) ENET_RX_DATA3,2,1,0 M3 M4 M1 M2 ENET_RX_ER ENET_RX_EN (inputs) |
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