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AT25DF512C-MAHN-T Datasheet(PDF) 5 Page - List of Unclassifed Manufacturers

Part # AT25DF512C-MAHN-T
Description  512-Kbit, 1.65V Minimum SPI Serial Flash Memory with Dual-I/O Support
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AT25DF512C-MAHN-T Datasheet(HTML) 5 Page - List of Unclassifed Manufacturers

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AT25DF512C
DS-25DF512C–030A–4/2014
4.
Memory Array
To provide the greatest flexibility, the memory array of the AT25DF512C can be erased in three levels of granularity
including a full chip erase. The size of the erase blocks is optimized for both code and data storage applications, allowing
both code and data segments to reside in their own erase regions. The Memory Architecture Diagram illustrates the
breakdown of each erase level.
Figure 4-1.
Memory Architecture Diagram
5.
Device Operation
The AT25DF512C is controlled by a set of instructions that are sent from a host controller, commonly referred to as the
SPI Master. The SPI Master communicates with the AT25DF512C via the SPI bus which is comprised of four signal lines:
Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO).
The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect to the
SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The AT25DF512C
supports the two most common modes, SPI Modes 0 and 3. The only difference between SPI Modes 0 and 3 is the
polarity of the SCK signal when in the inactive state (when the SPI Master is in standby mode and not transferring any
data). With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK and always output on the falling edge
of SCK.
32KB
4KB
1-256 Byte
Block Erase
Block Erase
Page Program
(52h Command)
(20h Command)
(02h Command)
4KB
00FFFFh – 00F000h
256 Bytes
00FFFFh – 00FF00h
4KB
00EFFFh – 00E000h
256 Bytes
00FEFFh – 00FE00h
4KB
00DFFFh – 00D000h
256 Bytes
00FDFFh – 00FD00h
4KB
00CFFFh – 00C000h
256 Bytes
00FCFFh – 00FC00h
4KB
00BFFFh – 00B000h
256 Bytes
00FBFFh – 00FB00h
4KB
00AFFFh – 00A000h
256 Bytes
00FAFFh – 00FA00h
4KB
009FFFh – 009000h
256 Bytes
00F9FFh – 00F900h
4KB
4KB
4KB
006FFFh – 006000h
256 Bytes
0006FFh – 000600h
4KB
005FFFh – 005000h
256 Bytes
0005FFh – 000500h
4KB
004FFFh – 004000h
256 Bytes
0004FFh – 000400h
4KB
003FFFh – 003000h
256 Bytes
0003FFh – 000300h
4KB
002FFFh – 002000h
256 Bytes
0002FFh – 000200h
4KB
001FFFh – 001000h
256 Bytes
0001FFh – 000100h
4KB
008FFFh – 008000h
007FFFh – 007000h
000FFFh – 000000h
256 Bytes
0000FFh – 000000h
Block Erase Detail
Page Program Detail
Page Address
Block Address
Range
Range
32KB
32KB


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