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FDMC8321L Datasheet(PDF) 4 Page - Fairchild Semiconductor |
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FDMC8321L Datasheet(HTML) 4 Page - Fairchild Semiconductor |
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4 / 7 page  www.fairchildsemi.com 4 FDMC8321L Rev.C2 Figure 7. 0 1020 3040 50 0 2 4 6 8 10 ID = 22 A VDD = 24 V VDD = 16 V Qg, GATE CHARGE (nC) VDD = 20 V Gate Charge Characteristics Figure 8. 0.1 1 10 40 10 100 1000 10000 f = 1 MHz VGS = 0 V VDS, DRAIN TO SOURCE VOLTAGE (V) Crss Coss Ciss Capacitance vs Drain to Source Voltage Figure9. 0.01 0.1 1 10 100 1 10 100 TJ = 100 oC TJ = 25 oC TJ = 125 oC t AV, TIME IN AVALANCHE (ms) UnclampedInductive Switching Capability Figure 10. 25 50 75 100 125 150 0 20 40 60 80 100 VGS = 4.5 V RθJC = 3.1 o C/W VGS = 10 V T C , CASE TEMPERATURE ( o C ) Limited by package Maximum Continuous Drain Current vs Case Temperature Figure 11. Forward Bias Safe Operating Area 0.01 0.1 1 10 100200 0.01 0.1 1 10 100 200 1 ms 1 s 10 ms DC 10 s 100 ms VDS, DRAIN to SOURCE VOLTAGE (V) THIS AREA IS LIMITED BY r DS(on) SINGLE PULSE TJ = MAX RATED RθJA = 125 oC/W TA = 25 oC Figure 12. 10 -3 10 -2 10 -1 110 100 1000 0.5 1 10 100 1000 SINGLE PULSE RθJA = 125 oC/W TA = 25 oC t, PULSE WIDTH (sec) Single Pulse Maximum Power Dissipation Typical Characteristics T J = 25 °C unless otherwise noted |
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Similar Description - FDMC8321L |
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