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4Mx16 DDR SDRAM

EM658160

Etron Confidential

11

Rev. 1.1

Jan. 2002

Note:

1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the

device.

3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the

4. Power-up sequence is described in Note 6.

5. A.C. Test Conditions

SSTL_2 Interface

Output Load

Reference to the Under Output Load (A)

Input Signal Levels

Input Signals Slew Rate

1 V/ns

Reference Level of Input Signals

25

Ω

Output

30pF

25

Ω

SSTL_2 A.C. Test Load

6.

Power up Sequence

Power up must be performed in the following sequence.

2) After power-up, No-Operation of 200

µ−seconds minimum is required.

3) Start clock and keep CKE “HIGH” to maintain either No-Operation or Device Deselect at the input.

4) Issue EMRS – enable DLL.

5) Issue MRS – reset DLL and set device to idle with bit A8 (An additional 200 cycles min of clock are

needed for DLL lock)

6) Precharge all banks of the device.

7) Two or more Auto Refresh commands.

8) Issue MRS – Initialize device operation.