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EM78P156E Datasheet(PDF) 3 Page - ELAN Microelectronics Corp

Part No. EM78P156E
Description  8-bit microprocessor with low-power and high-speed CMOS technology
Download  28 Pages
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Maker  EMC [ELAN Microelectronics Corp]
Homepage  http://www.emc.com.tw

EM78P156E Datasheet(HTML) 3 Page - ELAN Microelectronics Corp

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* This specification is subject to be changed without notice. 8.11.1999
VI.1 Operational Registers
R0 (Indirect Addressing Register)
• R0 is not a physically implemented register. Its major function is to be an indirect addressing pointer. Any instruction
using R0 as a pointer actually accesses data pointed by the RAM Select Register (R4).
R1 (Time Clock /Counter)
• Increased by an external signal edge which is defined by TE bit (CONT-4) through the TCC pin,
or by the instruction cycle clock.
• Writable and readable as any other registers.
R2 (Program Counter) & Stack
• R2 and hardware stacks are 10~12-bit wide. The structure is depicted in Fig. 3.
• Generating 1024x13 bits on-chip OTP ROM addresses to the relative programming instruction codes. One program
page is 1024 words long.
• The contents of R2 are set all “0”s upon a RESET condition.
• “JMP” instruction allows the direct loading of the lower 10 program counter bits. Thus, “JMP” allows PC to go to
any location within a page.
• “CALL” instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus, the subroutine
entry address can locate anywhere within a page.
“ RET” (“RETL K”, “RETI”) instruction loads the program counter with the contents of the top-level stack.
“ADD R2,A” allows a relative address to be added to the current PC, and the ninth and tenth bits of the PC are cleared.
• “MOV R2,A” allows to load an address from the “A” register to the lower 8 bits of the PC, and the ninth and tenth
bits of the PC are cleared.
• Any instruction which would change the contents of R2 (e.g. “ADD R2,A”, “MOV R2,A”, “BC R2,6”,......) will
cause the ninth and tenth bits (A8~A9) of the PC to be cleared. Thus, the computed jump is limited to the first
256 locations of a page.
• All instructions are single instruction cycle (fclk/2) except the instructions which would change the contents of R2
need one more instruction cycle.
* Input pin with Schmitt trigger. If this pin remains at logic low, the controller
will keep in reset condition.
* P50~P53 are bi-directional I/O pins. P50 and P51 can also be defined as the
R-option pins. P50~P52 can be pulled down by software .
* P60~P67 are bi-directional I/O pins. These can be pull-high or can be open-
drain by software programming. In addition, P60~P63 can be pull-down
also by software.
* External interrupt pin triggered by falling edge.
* Power supply.
* Ground.

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