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PD488588 Datasheet(PDF) 1 Page - Elpida Memory

Part # PD488588
Description  288M bits Direct Rambus DRAM
Download  79 Pages
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Manufacturer  ELPIDA [Elpida Memory]
Direct Link  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

PD488588 Datasheet(HTML) 1 Page - Elpida Memory

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Document No. E0039N30 (Ver. 3.0)
Date Published July 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2001-2002
NEC Corporation 2000
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
DATA SHEET
288M bits Direct Rambus DRAM
µµµµPD488588 (512K words ×××× 18 bits ×××× 32s banks)
Description
The Direct Rambus DRAM (Direct RDRAM) is a
general purpose high-performance memory device
suitable for use in a broad range of applications
including computer memory, graphics, video, and any
other application where high bandwidth and low
latency are required.
The
µPD488588 is 288Mbits Direct Rambus DRAM
(RDRAM), organized as 16M words by 18 bits.
The use of Rambus Signaling Level (RSL) technology
permits 600MHz to 800MHz transfer rates while using
conventional system and board design technologies.
Direct RDRAM devices are capable of sustained data
transfers at 1.25ns per two bytes (10ns per sixteen
bytes).
The architecture of the Direct RDRAMs allows the
highest sustained bandwidth for multiple, simultaneous
randomly addressed memory transactions.
The separate control and data buses with independent
row and column control yield over 95% bus efficiency.
The Direct RDRAM’s four banks support up to four
simultaneous transactions.
System oriented features for mobile, graphics and
large memory systems include power management,
byte masking.
The
µPD488588 is offered in a CSP horizontal
package suitable for desktop as well as low-profile
add-in card and mobile applications. Direct RDRAMs
operate from a 2.5V supply.
Features
• Highest sustained bandwidth per DRAM device
— 1.6 GB/s sustained data transfer rate
— Separate control and data buses for maximized
efficiency
— Separate row and column control buses for easy
scheduling and highest performance
— 32 banks: four transactions can take place
simultaneously at full bandwidth data rates
• Low latency features
— Write buffer to reduce read latency
— 3 precharge mechanisms for controller flexibility
— Interleaved transactions
• Advanced power management:
— Multiple low power states allows flexibility in power
consumption versus time to active state
— Power-down self-refresh
• Overdrive current mode
• Organization: 2K bytes pages and 32 banks, x 18
• Uses Rambus Signaling Level (RSL) for up to
800MHz operation
• Package : 80-ball FBGA (
µBGA) (17.16 × 10.2)


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