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MC-4R256FKK6K-840 Datasheet(PDF) 4 Page - Elpida Memory |
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MC-4R256FKK6K-840 Datasheet(HTML) 4 Page - Elpida Memory |
4 / 13 page MC-4R256FKK6K Preliminary Data Sheet E0268N10 (Ver. 1.0) 4 Module Connector Pad Description Signal Module connector pads I/O Type Description CFM_THRU_L A14 I RSL Clock From Master. Connects to left RDRAM device on "Thru" Channel. Interface clock used for receiving RSL signals from the controller. Positive polarity. CFM_THRU_R B54 I RSL Clock From Master. Connects to right RDRAM device on "Thru" Channel. Interface clock used for receiving RSL signals from the controller. Positive polarity. CFMN_THRU_L A16 I RSL Clock From Master. Connects to left RDRAM device on "Thru" Channel. Interface clock used for receiving RSL signals from the controller. Negative polarity. CFMN_THRU_R B52 I RSL Clock From Master. Connects to right RDRAM device on "Thru" Channel. Interface clock used for receiving RSL signals from the controller. Negative polarity. CMD_THRU_L B2 I VCMOS Serial Command Input used to read from and write to the control registers. Also used for power management. Connects to left RDRAM device on "Thru" Channel. CMD_THRU_R A73 I VCMOS Serial Command Input used to read from and write to the control registers. Also used for power management. Connects to right RDRAM device on "Thru" Channel. COL4_THRU_L.. COL0_THRU_L A20, B20, A22, B22, A24 I RSL "Thru" Channel Column bus. 5-bit bus containing control and address information for column accesses. Connects to left RDRAM device on "Thru" Channel. COL4_THRU_R.. COL0_THRU_R B48, A48, B46, A46, B44 I RSL "Thru" Channel Column bus. 5-bit bus containing control and address information for column accesses. Connects to right RDRAM device on "Thru" Channel. CTM_THRU_L B14 I RSL Clock To Master. Connects to left RDRAM device on "Thru" Channel. Interface clock used for transmitting RSL signals to the controller. Positive polarity. CTM_THRU_R A54 I RSL Clock To Master. Connects to right RDRAM device on "Thru" Channel. Interface clock used for transmitting RSL signals to the controller. Positive polarity. CTMN_THRU_L B12 I RSL Clock To Master. Connects to left RDRAM device on "Thru" Channel. Interface clock used for transmitting RSL signals to the controller. Negative polarity. CTMN_THRU_R A56 I RSL Clock To Master. Connects to right RDRAM device on "Thru" Channel. Interface clock used for transmitting RSL signals to the controller. Negative polarity. DQA8_THRU_L.. DQA0_THRU_L A4, B4, A6, B6, A8, B8, A10, B10, A12 I/O RSL "Thru" Channel Data bus A. A 9-bit bus carrying a byte of read or write data between the controller and RDRAM devices on “Thru” Channel. Connects to left RDRAM device on "Thru" Channel. DQA8_THRU_L is non-functional on modules. DQA8_THRU_R.. DQA0_THRU_R B67, A67, B65, A65, B63, A63, B58, A58, B56 I/O RSL "Thru" Channel Data bus A. A 9-bit bus carrying a byte of read or write data between the controller and RDRAM devices on “Thru” Channel. Connects to right RDRAM device on "Thru" Channel. DQA8_THRU_R is non-functional on modules. DQB8_THRU_L.. DQB0_THRU_L B32, A32, B30, A30, B28, A28, B26, A26, B24 I/O RSL "Thru" Channel Data bus B. A 9-bit bus carrying a byte of read or write data between the controller and RDRAM devices on “Thru” Channel. Connects to left RDRAM device on "Thru" Channel. DQB8_THRU_L is non-functional on modules. DQB8_THRU_R.. DQB0_THRU_R A36, B36, A38, B38, A40, B40, A42, B42, A44 I/O RSL "Thru" Channel Data bus B. A 9-bit bus carrying a byte of read or write data between the controller and RDRAM devices on “Thru” Channel. Connects to right RDRAM device on "Thru" Channel. DQB8_THRU_R is non-functional on modules. ROW2_THRU_L.. ROW0_THRU_L B16, A18, B18 I RSL Row bus. 3-bit bus containing control and address information for row accesses. Connects to left RDRAM device on "Thru" Channel. |
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