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HB54A5129F1U Datasheet(PDF) 5 Page - Elpida Memory

Part No. HB54A5129F1U
Description  512MB Registered DDR SDRAM DIMM
Download  16 Pages
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Maker  ELPIDA [Elpida Memory]
Homepage  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

HB54A5129F1U Datasheet(HTML) 5 Page - Elpida Memory

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HB54A5129F1U-A75B/B75B/10B
Data Sheet E0191H30 (Ver. 3.0)
5
Serial PD Matrix*
1
Byte No.
Function described
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Hex value
Comments
0
Number of bytes utilized by module
manufacturer
1
0
0
0
0
0
0
0
80
128
1
Total number of bytes in serial PD
device
0
0
0
0
1
0
0
0
08
256 byte
2
Memory type
0
0
0
0
0
1
1
1
07
SDRAM DDR
3
Number of row address
0
0
0
0
1
1
0
1
0D
13
4
Number of column address
0
0
0
0
1
0
1
1
0B
11
5
Number of DIMM banks
0
0
0
0
0
0
0
1
01
1
6
Module data width
0
1
0
0
1
0
0
0
48
72 bits
7
Module data width continuation
0
0
0
0
0
0
0
0
00
0 (+)
8
Voltage interface level of this assembly 0
0
0
0
0
1
0
0
04
SSTL 2.5V
9
DDR SDRAM cycle time, CL = X
-A75B
0
1
1
1
0
0
0
0
70
CL = 2.5*
5
-B75B
0
1
1
1
0
1
0
1
75
-10B
1
0
0
0
0
0
0
0
80
10
SDRAM access from clock (tAC)
-A75B/B75B
0
1
1
1
0
1
0
1
75
0.75ns*
5
-10B
1
0
0
0
0
0
0
0
80
0.8ns*
5
11
DIMM configuration type
0
0
0
0
0
0
1
0
02
ECC
12
Refresh rate/type
1
0
0
0
0
0
1
0
82
7.8 µs
Self refresh
13
Primary SDRAM width
0
0
0
0
0
1
0
0
04
× 4
14
Error checking SDRAM width
0
0
0
0
0
1
0
0
04
× 4
15
SDRAM device attributes:
Minimum clock delay back-to-back
column access
0
0
0
0
0
0
0
1
01
1 CLK
16
SDRAM device attributes:
Burst length supported
0
0
0
0
1
1
1
0
0E
2, 4, 8
17
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04
4
18
SDRAM device attributes:
/CAS latency
0
0
0
0
1
1
0
0
0C
2/2.5
19
SDRAM device attributes:
/CS latency
0
0
0
0
0
0
0
1
01
0
20
SDRAM device attributes:
/WE latency
0
0
0
0
0
0
1
0
02
1
21
SDRAM module attributes
0
0
1
0
0
1
1
0
26
Registered
22
SDRAM device attributes: General
1
1
0
0
0
0
0
0
C0
± 0.2V
23
Minimum clock cycle time at
CLX - 0.5
-A75B
0
1
1
1
0
1
0
1
75
CL = 2*
5
-B75B/10B
1
0
1
0
0
0
0
0
A0
24
Maximum data access time (tAC) from
clock at CLX - 0.5
-A75B/B75B
0
1
1
1
0
1
0
1
75
0.75ns*
5
-10B
1
0
0
0
0
0
0
0
80
0.8ns*
5
25
Minimum clock cycle time at
CLX - 1
0
0
0
0
0
0
0
0
00
26
Maximum data access time (tAC) from
clock at CLX - 1
0
0
0
0
0
0
0
0
00
27
Minimum row precharge time (tRP)
0
1
0
1
0
0
0
0
50
20ns


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