HB52RF648DC-B, HB52RD648DC-B

Data Sheet E0083H40

18

Pin Functions

CK0/CK1 (input pin): CK is the master clock input to this pin. The other input signals are referred at CK

rising edge.

S0/S1 (input pin): When S is Low, the command input cycle becomes valid. When S is High, all inputs are

ignored. However, internal operations (bank active, burst operations, etc.) are held.

RE, CE and W (input pins): Although these pin names are the same as those of conventional DRAM

modules, they function in a different way. These pins define operation commands (read, write, etc.)

depending on the combination of their voltage levels. For details, refer to the command operation section.

A0 to A12 (input pins): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active

command cycle CK rising edge. Column address (AY0 to AY9) is determined by A0 to A9 level at the read

or write command cycle CK rising edge. And this column address becomes burst access start address. A10

defines the precharge mode. When A10 = High at the precharge command cycle, both banks are precharged.

But when A10 = Low at the precharge command cycle, only the bank that is selected by BA0/BA1 (BA) is

precharged.

BA0/BA1 (input pin): BA0/BA1 is a bank select signal (BA). The memory array is divided into bank0,

bank1, bank2 and bank3. If BA0 is Low and BA1 is Low, bank0 is selected. If BA0 is High and BA1 is

Low, bank1 is selected. If BA0 is Low and BA1 is High, bank2 is selected. If BA0 is High and BA1 is High,

bank3 is selected.

CKE0, CKE1 (input pin): This pin determines whether or not the next CK is valid. If CKE is High, the

next CK rising edge is valid. If CKE is Low, the next CK rising edge is invalid. This pin is used for power-

down mode, clock suspend mode and self refresh mode.

DQMB0 to DQMB7 (input pins): Read operation: If DQMB is High, the output buffer becomes High-Z. If

the DQMB is Low, the output buffer becomes Low-Z (The latency of DQMB during reading is 2 clocks).

Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is Low,

the data is written (The latency of DQMB during writing is 0 clock).

DQ0 to DQ63 (DQ pins): Data is input to and output from these pins.

V

V

Detailed Operation Part

Refer to the HM5225165B/HM5225805B/HM5225405B-75/A6/B6 datasheet (E0082H).