EDE5104GBSA datasheet(30/56 Pages) ELPIDA

Part #	EDE5104GBSA

Description	512M bits DDR-II SDRAM

Download	56 Pages

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Manufacturer	ELPIDA [Elpida Memory]

Direct Link	http://www.elpida.com/en

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30 / 56 page

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

Preliminary Data Sheet E0249E30 (Ver. 3.0)

30

ODT Control of Reads

At a minimum, ODT must be latched High by CK at (Read Latency – 3tCK) after the READ command and remain

High until (Read Latency

+ BL/2 – 2tCK) after the READ command (where Read Latency = AL + CL). The controller

is also required to activate it´s own termination with a turn on time the same as the DRAM and keeping it on until

valid data is no longer on the system bus.

CK

/CK

T0

T1

T2

T3

T4

T5

T6

ODT

at DRAM in slot2

at DRAM in slot1

Controller

Term Res.

DRAM

Term Res.

Rtt (DRAM)

Rtt (Controller)

Command

(to slot1)

ODT

(to slot2)

NOP

READ

Command

DQ

DQS

READ

out0

out1

out2

out3

tAOND

tAOFD

RL

NOP

Read Example for a 2 Slot Registered System with 2nd Slot in Active Mode

(Read Latency

==== 3tCK ;;;; tAOND ==== 2tCK ;;;; tAOFD ==== 2.5tCK)

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EDE5104GBSA Datasheet(PDF) 30 Page - Elpida Memory

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