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EBS26UC6APS Datasheet(PDF) 10 Page - Elpida Memory |
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EBS26UC6APS Datasheet(HTML) 10 Page - Elpida Memory |
10 / 14 page EBS26UC6APS Data Sheet E0225E20 (Ver. 2.0) 10 Test Conditions • Input and output timing reference levels: 1.4V • Input waveform and output load: See following figures tT 2.4V 0.4V 0.8V 2.0V tT DQ CL Input Waveform and Output Load Relationship Between Frequency and Minimum Latency (SDRAM device specification) Parameter -7A/7AL -75/75L -80/80L Frequency (MHz) 133 133 10 tCK (ns) 7.5 7.5 10 /CAS latency Symbol CL = 2 CL = 3 CL = 2 Notes Active command to column command (same bank) lRCD 2 3 2 1 Active command to active command (same bank) lRC 8 9 7 1 Active command to precharge command (same bank) lRAS 6 6 5 1 Precharge command to active command (same bank) lRP 2 3 2 1 Write recovery or data-in to precharge command (same bank) lDPL 2 2 2 1 Active command to active command (different bank) lRRD 2 2 2 1 Self refresh exit time lSREX 1 1 1 2 Last data in to active command (Auto precharge, same bank) lDAL 4 5 4 = [lDPL + lRP] Self refresh exit to command input lSEC 8 9 7 = [lRC] 3 Precharge command to high impedance lHZP 2 3 2 Last data out to active command (auto precharge) (same bank) lAPR 1 1 1 Last data out to precharge (early precharge) lEP –1 –2 –1 Column command to column command lCCD 1 1 1 Write command to data in latency lWCD 0 0 0 DQM to data in lDID 0 0 0 DQM to data out lDOD 2 2 2 CKE to CLK disable lCLE 1 1 1 Register set to active command lMRD 2 2 2 /CS to command disable lCDD 0 0 0 Power down exit to command input lPEC 1 1 1 Notes: 1. IRCD to IRRD are recommended value. 2. Be valid [DESL] or [NOP] at next command of self refresh exit. 3. Except [DESL] and [NOP] |
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