EBS26UC6APS

Data Sheet E0225E20 (Ver. 2.0)

9

Pin Capacitance (TA = +25°C, VDD = 3.3V ± 0.3V)

Parameter

Symbol

Pins

max.

Unit

Notes

Input capacitance

CI1

Address

TBD

pF

1, 2, 4

CI2

/RAS, /CAS, /WE

TBD

pF

1, 2, 4

CI3

CKE

TBD

pF

1, 2, 4

CI4

/CS

TBD

pF

1, 2, 4

CI5

CLK

TBD

pF

1, 2, 4

CI6

DQMB

TBD

pF

1, 2, 4

Data input/output capacitance

CI/O1

DQ

TBD

pF

1, 2, 3, 4

AC Characteristics (TA = 0 to +70°C, VDD = 3.3V ± 0.3V, VSS = 0V) (SDRAM device specification)

-7A/7AL

-75/75L

-80/80L

Parameter

Symbol min.

max.

min.

max.

min.

max.

Unit

Notes

System clock cycle time

(CL = 2)

tCK

7.5

—

10

—

10

—

ns

1

(CL = 3)

tCK

7.5

—

7.5

—

10

—

ns

CLK high pulse width

tCH

2.5

—

2.5

—

3

—

ns

1

CLK low pulse width

tCL

2.5

—

2.5

—

3

—

ns

1

Access time from CLK

tAC

—

5.4

—

5.4

—

6

ns

1, 2

Data-out hold time

tOH

2.7

—

2.7

—

2.7

—

ns

1, 2

CLK to Data-out low impedance

tLZ

1

—

1

—

1

—

ns

1, 2, 3

CLK to Data-out high impedance

tHZ

—

5.4

—

5.4

—

6

ns

1, 4

Input setup time

tSI

1.5

—

1.5

—

2

—

ns

1

Input hold time

tHI

0.8

—

0.8

—

1

—

ns

1

Ref/Active to Ref/Active command period tRC

60

—

67.5

—

70

—

ns

1

Active to Precharge command period

tRAS

45

120000 45

120000 48

120000 ns

1

Active command to column command

(same bank)

tRCD

15

—

20

—

20

—

ns

1

Precharge to active command period

tRP

15

—

20

—

20

—

ns

1

Write recovery or data-in to precharge

lead time

tDPL

15

—

15

—

20

—

ns

1

Last data into active latency

tDAL

2CLK +

15ns

—

2CLK +

20ns

—

2CLK +

20ns

—

Active (a) to Active (b) command period

tRRD

15

—

15

—

20

—

ns

1

Transition time (rise and fall)

tT

0.5

5

0.5

5

0.5

5

ns

Refresh period

(8192 refresh cycles)

tREF

—

64

—

64

—

64

ms

Notes: 1. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.4V.

3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.

4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.