Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

EBD11ED8ABFB Datasheet(PDF) 1 Page - Elpida Memory

Part No. EBD11ED8ABFB
Description  1GB Unbuffered DDR SDRAM DIMM EBD11ED8ABFB (128M words × 72 bits, 2 Banks)
Download  19 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  ELPIDA [Elpida Memory]
Direct Link  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

EBD11ED8ABFB Datasheet(HTML) 1 Page - Elpida Memory

  EBD11ED8ABFB Datasheet HTML 1Page - Elpida Memory EBD11ED8ABFB Datasheet HTML 2Page - Elpida Memory EBD11ED8ABFB Datasheet HTML 3Page - Elpida Memory EBD11ED8ABFB Datasheet HTML 4Page - Elpida Memory EBD11ED8ABFB Datasheet HTML 5Page - Elpida Memory EBD11ED8ABFB Datasheet HTML 6Page - Elpida Memory EBD11ED8ABFB Datasheet HTML 7Page - Elpida Memory EBD11ED8ABFB Datasheet HTML 8Page - Elpida Memory EBD11ED8ABFB Datasheet HTML 9Page - Elpida Memory Next Button
Zoom Inzoom in Zoom Outzoom out
 1 / 19 page
background image
Document No. E0295E20 (Ver. 2.0)
Date Published August 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory , Inc. 2002
PRELIMINARY DATA SHEET
1GB Unbuffered DDR SDRAM DIMM
EBD11ED8ABFB (128M words
×××× 72 bits, 2 Banks)
Description
The EBD11ED8ABFB is 128M words
× 72 bits, 2
banks Double Data Rate (DDR) SDRAM unbuffered
module, mounted 18 pieces of 512M bits DDR SDRAM
sealed in TSOP package. Read and write operations
are performed at the cross points of the CK and the
/CK. This high-speed data transfer is realized by the 2
bits prefetch-pipelined architecture. Data strobe (DQS)
both for read and write are available for high speed and
reliable data bus design. By setting extended mode
register, the on-chip Delay Locked Loop (DLL) can be
set enable or disable.
This module provides high
density mounting without utilizing surface mount
technology.
Decoupling capacitors are mounted
beside each TSOP on the module board.
Features
• 184-pin socket type dual in line memory module
(DIMM)
 PCB height: 31.75mm
 Lead pitch: 1.27mm
• 2.5V power supply
• Data rate: 333Mbps/266Mbps (max.)
• 2.5 V (SSTL_2 compatible) I/O
• Double Data Rate architecture; two data transfers per
clock cycle
• Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
• Data inputs and outputs are synchronized with DQS
• 4 internal banks for concurrent operation
(Component)
• DQS is edge aligned with data for READs; center
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
referenced to both edges of DQS
• Auto precharge option for each burst access
• Programmable burst length: 2, 4, 8
• Programmable /CAS latency (CL): 2, 2.5
• Refresh cycles: (8192 refresh cycles /64ms)
 7.8µs maximum average periodic refresh interval
• 2 variations of refresh
 Auto refresh
 Self refresh


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19 


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn