SATA-Disk Module 4

APSDMxxxx15XX-PXX

9

© 2013 Apacer Technology Inc.

Rev. 1.4

5. Flash Management

5.1 Error Correction/Detection

SDM4 implements a hardware ECC scheme, based on the BCH algorithm. It can detect and correct up to

16 bits or 24 bits error in 1K bytes.

5.2 Bad Block Management

Current production technology is unable to guarantee total reliability of NAND flash memory array. When

a flash memory device leaves factory, it comes with a minimal number of initial bad blocks during

production or out-of-factory as there is no currently known technology that produce flash chips free of bad

blocks. In addition, bad blocks may develop during program/erase cycles. When host performs

program/erase command on a block, bad block may appear in Status Register. Since bad blocks are

inevitable, the solution is to keep them in control. Apacer flash devices are programmed with ECC, block

mapping technique and S.M.A.R.T to reduce invalidity or error. Once bad blocks are detected, data in

those blocks will be transferred to free blocks and error will be corrected by designated algorithms.

5.3 Wear Leveling

Flash memory devices differ from Hard Disk Drives (HDDs) in terms of how blocks are utilized. For HDDs,

when a change is made to stored data, like erase or update, the controller mechanism on HDDs will

perform overwrites on blocks. Unlike HDDs, flash blocks cannot be overwritten and each P/E cycle wears

down the lifespan of blocks gradually. Repeatedly program/erase cycles performed on the same memory

cells will eventually cause some blocks to age faster than others. This would bring flash storages to their

end of service term sooner. Wear leveling is an important mechanism that level out the wearing of blocks

so that the wearing-down of blocks can be almost evenly distributed. This will increase the lifespan of

SSDs. Commonly used wear leveling types are Static and Dynamic.

5.4 Power Failure Management

Power Failure Management plays a crucial role when experiencing unstable power supply. Power

disruption may occur when users are storing data into the SSD. In this urgent situation, the controller

would run multiple write-to-flash cycles to store the metadata for later block rebuilding. This urgent

operation requires about several milliseconds to get it done. At the next power up, the firmware will

perform a status tracking to retrieve the mapping table and resume previously programmed NAND blocks

to check if there is any incompleteness of transmission.

5.5 ATA Secure Erase

ATA Secure Erase is an ATA disk purging command currently embedded in most of the storage drives.

Defined in ATA specifications, (ATA) Secure Erase is part of Security Feature Set that allows storage

drives to erase all user data areas. The erase process usually runs on the firmware level as most of the

ATA-based storage media currently in the market are built-in with this command. ATA Secure Erase can

securely wipe out the user data in the drive and protects it from malicious attack.