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IDT7006SL Datasheet(PDF) 13 Page - Integrated Device Technology

Part No. IDT7006SL
Description  HIGH-SPEED HIGH-SPEED STATIC RAM
Download  20 Pages
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT7006SL Datasheet(HTML) 13 Page - Integrated Device Technology

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6.42
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
13
Timing Waveform of Write with Port-to-Port Read and BUSY(2,5)(M/S = VIH)(4)
Timing Waveform of Write with BUSY
NOTES:
1. tWH must be met for both
BUSY input (slave) and output (master).
2.
BUSY is asserted on Port "B", blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the 'Slave' Version.
2739 drw 13
tDW
tAPS
(1)
ADDR"A"
tWC
DATAOUT "B"
MATCH
tWP
R/
W"A"
DATAIN "A"
ADDR"B"
tDH
VALID
MATCH
BUSY"B"
tBDA
VALID
tBDD
tDDD
(3)
tWDD
2739 drw 14
R/
W"A"
BUSY"B"
tWP
tWB
(3)
R/
W"B"
tWH
(1)
(2)
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2.
CEL = CER = VIL
3.
OE = VIL for the reading port.
4.
If M/
S = VIL(slave) then BUSY is input (BUSY"A" = VIH) and BUSY"B" = "don't care", for this example.
5.
All timing is the same for left and right port. Port "A' may be either left or right port. Port "B" is the port opposite from Port "A".


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