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IDT7006SL Datasheet(PDF) 8 Page - Integrated Device Technology

Part No. IDT7006SL
Description  HIGH-SPEED HIGH-SPEED STATIC RAM
Download  20 Pages
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT7006SL Datasheet(HTML) 8 Page - Integrated Device Technology

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IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing of Power-Up Power-Down
Waveform of Read Cycles(5)
NOTES:
1. Timing depends on which signal is asserted last,
OE or CE.
2. Timing depends on which signal is de-asserted first
CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5.
SEM = VIH.
tRC
R/
W
CE
ADDR
tAA
(4)
OE
2739 drw 07
tACE
(4)
tAOE
(4)
tLZ
(1)
tOH
tHZ
(2)
tBDD
(3,4)
DATAOUT
BUSYOUT
VALID DATA
(4)
CE
2739 drw 08
tPU
ICC
ISB
tPD
,


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