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IDT7006SL Datasheet(PDF) 19 Page - Integrated Device Technology
IDT [Integrated Device Technology]
IDT7006SL Datasheet(HTML) 19 Page - Integrated Device Technology
/ 20 page
High-Speed 16K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
to indicate the side which would control the lower section of memory, and
Semaphore 1 could be defined as the indicator for the upper section of
To take a resource, in this example the lower 8K of Dual-Port RAM,
the processor on the left port could write and then read a zero in to
Semaphore 0. If this task were successfully completed (a zero was read
back rather than a one), the left processor would assume control of the
to the zero it had attempted to write into Semaphore 0. At this point, the
software could choose to try and gain control of the second 8K section by
writing, then reading a zero into Semaphore 1. If it succeeded in gaining
control, it would lock out the left side.
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore 1 was still occupied by the right side, the left side could undo
with Semaphore 0, this protocol would allow the two processors to swap
8K blocks of Dual-Port RAM with each other.
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
semaphore flags. All eight semaphores could be used to divide the Dual-
Port RAM or other shared resources into eight parts. Semaphores can
even be assigned different meanings on different sides rather than being
given a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like disk
a transfer and the I/O device cannot tolerate any wait states. With the use
their assigned portions of memory continuously without any wait states.
been performed, both processors can access their assigned RAM
segments at full speed.
Another application is in the area of complex data structures. In this
may be responsible for building and updating a data structure. The other
processor then reads and interprets that data structure. If the interpreting
exist. Therefore, some sort of arbitration must be used between the two
it and then is able to go in and update the data structure. When the update
is completed, the data structure block is released. This allows the
thereby guaranteeing a consistent data structure.
Figure 4. IDT7006 Semaphore Logic
2739 drw 20
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