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IDT7006SL Datasheet(PDF) 17 Page - Integrated Device Technology

Part No. IDT7006SL
Description  HIGH-SPEED HIGH-SPEED STATIC RAM
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT7006SL Datasheet(HTML) 17 Page - Integrated Device Technology

 
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6.42
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
17
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7006 RAMs.
haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe
twoaccessestoproceedandsignalstheothersidethattheRAMis“busy”.
The
BUSY pincanthenbeusedtostalltheaccessuntiltheoperationon
the other side is completed. If a write operation has been attempted from
thesidethatreceivesa
BUSYindication,thewritesignalisgatedinternally
to prevent the write from proceeding.
The use of
BUSYlogicisnotrequiredordesirableforallapplications.
In some cases it may be useful to logically OR the
BUSYoutputstogether
and use any
BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of
BUSYlogicis
not desirable, the
BUSYlogiccanbedisabledbyplacingthepartinslave
mode with the M/
Spin.OnceinslavemodetheBUSYpinoperatessolely
as a write inhibit input pin. Normal operation can be programmed by tying
the
BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the
BUSY pin for that port LOW.
The
BUSY outputs on the IDT 7006 RAM in master mode, are push-
pull type outputs and do not require pull up resistors to operate. If these
RAMs are being expanded in depth, then the
BUSY indication for the
resulting array requires the use of an external AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an IDT7006 RAM array in width while using
BUSY
logic, one master part is used to decide which side of the RAMs array will
receive a
BUSYindication, and to output that indication. Any number of
slaves to be addressed in the same address range as the master, use the
BUSYsignalasawriteinhibitsignal.ThusontheIDT7006RAMtheBUSY
pinisanoutputifthepartisusedasamaster(M/
Spin=VIH),andtheBUSY
pin is an input if the part used as a slave (M/
S pin = VIL) as shown in
Figure 3.
Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit
decision could result with one master indicating
BUSYononesideofthe
array and another master indicating BUSY on one other side of the array.
This would inhibit the write operations from one port for part of a word and
inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.
The
BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enoughfora
BUSYflagtobeoutputfromthemasterbeforetheactualwrite
pulsecanbeinitiatedwiththeR/Wsignal.Failuretoobservethistimingcan
result in a glitched internal write inhibit signal and corrupted data in the
slave.
SEMAPHORES
TheIDT7006isanextremelyfastDual-Port16Kx8CMOSStaticRAM
withanadditional8addresslocationsdedicatedtobinarysemaphoreflags.
These flags allow either processor on the left or right side of the Dual-Port
RAM to claim a privilege over the other processor for functions defined by
the system designer’s software. As an example, the semaphore can be
used by one processor to inhibit the other from accessing a portion of the
Dual-Port RAM or any other shared resource.
The Dual-Port RAM features a fast access time, and both ports are
completely independent of each other. This means that the activity on the
left port in no way slows the access time of the right port. Both ports are
identical in function to standard CMOS Static RAM and can be read from,
orwrittento,atthesametimewiththeonlypossibleconflictarisingfromthe
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphorelocation.Semaphoresareprotectedagainstsuchambiguous
situations and may be used by the system program to avoid any conflicts
inthenon-semaphoreportionoftheDual-PortRAM.Thesedeviceshave
an automatic power-down feature controlled by
CE,theDual-PortRAM
enable, and
SEM,thesemaphoreenable.TheCE and SEMpinscontrol
on-chip power down circuitry that permits the respective port to go into
standby mode when not selected. This is the condition which is shown in
Truth Table I where
CE and SEM are both HIGH.
SystemswhichcanbestusetheIDT7006containmultipleprocessors
or controllers and are typically very high-speed systems which are
softwarecontrolledorsoftwareintensive.Thesesystemscanbenefitfrom
aperformanceincreaseofferedbytheIDT7006shardwaresemaphores,
which provide a lockout mechanism without requiring complex program-
ming.
Software handshaking between processors offers the maximum in
systemflexibilitybypermittingsharedresourcestobeallocatedinvarying
configurations. The IDT7006 does not use its semaphore flags to control
2739 drw 19
MASTER
Dual Port
RAM
BUSY (L) BUSY (R)
CE
MASTER
Dual Port
RAM
BUSY (L) BUSY (R)
CE
SLAVE
Dual Port
RAM
BUSY (L) BUSY (R)
CE
SLAVE
Dual Port
RAM
BUSY (L) BUSY (R)
CE
BUSY (L)
BUSY (R)


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