5

FN3586.10

June 4, 2007

Test Circuits and Waveforms

edge of the output waveform.

FIGURE 1A. MEASUREMENT POINTS

FIGURE 1B. TEST CIRCUIT

FIGURE 1. SWITCHING TIMES

FIGURE 2A. MEASUREMENT POINTS

FIGURE 2B. TEST CIRCUIT

FIGURE 2. CHARGE INJECTION

FIGURE 3. CROSSTALK TEST CIRCUIT

FIGURE 4. OFF ISOLATION TEST CIRCUIT

NOTE: Logic input waveform is inverted for switches that have

the opposite logic sense.

50%

80%

3V

0V

0V

LOGIC

INPUT

SWITCH

INPUT

SWITCH

OUTPUT

80%

Repeat test for Channels 2, 3 and 4.

stray capacitance.

V

O

V

S

R

L

R

L

r

DS ON

()

+

------------------------------------

=

SWITCH

INPUT

LOGIC

INPUT

3V

V+

GND

V-

SWITCH

OFF

ON

OFF

OFF

OFF

ON

Q =

(DG444)

(DG445)

OUTPUT

V+

GND

V-

0V, 2.4V

ANALYZER

+15V

V+

C

10dBm

SIGNAL

GENERATOR

GND

50

Ω

0V, 2.4V

NC

V-

-15V

C

ANALYZER

+15V

10dBm

SIGNAL

GENERATOR

V+

C

V-

-15V

C

0V, 2.4V

GND

DG444, DG445