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OMAP3503 Datasheet(PDF) 48 Page - Texas Instruments

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Part # OMAP3503
Description  OMAP3515 and OMAP3503 Applications Processors
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

OMAP3503 Datasheet(HTML) 48 Page - Texas Instruments

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OMAP3515, OMAP3503
SPRS505H – FEBRUARY 2008 – REVISED OCTOBER 2013
www.ti.com
Table 2-2. Ball Characteristics (CBC Pkg.)(1) (continued)
BALL
BALL
BUFFER
PULLUP
BALL
BALL TOP
PIN NAME
RESET REL.
MODE [4]
TYPE [5]
RESET
RESET REL.
POWER [9]
HYS [10]
STRENG TH
/DOWN
IO CELL [13]
BOTTOM [1]
[2]
[3]
MODE [8]
STATE [6]
STATE [7]
(mA) [11]
TYPE [12]
NA
U20
sdrc_ncas
0
O
1
1
0
vdds
No
4
(3)
NA
LVCMOS
NA
B13
sdrc_nclk
0
O
1
1
0
vdds
No
4
(3)
NA
LVCMOS
NA
T21
sdrc_ncs0
0
O
1
1
0
vdds
No
4
(3)
NA
LVCMOS
NA
T20
sdrc_ncs1
0
O
1
1
0
vdds
No
4
(3)
NA
LVCMOS
NA
V21
sdrc_nras
0
O
1
1
0
vdds
No
4
(3)
NA
LVCMOS
NA
Y18
sdrc_nwe
0
O
1
1
0
vdds
No
4
(3)
NA
LVCMOS
AE21
NA
dss_data0
0
IO
L
L
7
vdds
No
4
PU100/
LVCMOS
PD100
uart1_cts
2
I
gpio_70
4
IO
safe_mode
7
-
AE22
NA
dss_data1
0
IO
L
L
7
vdds
No
4
PU100/
LVCMOS
PD100
uart1_rts
2
O
gpio_71
4
IO
safe_mode
7
-
AE23
NA
dss_data2
0
IO
L
L
7
vdds
No
4
PU100/
LVCMOS
PD100
gpio_72
4
IO
safe_mode
7
-
AE24
NA
dss_data3
0
IO
L
L
7
vdds
No
4
PU100/
LVCMOS
PD100
gpio_73
4
IO
safe_mode
7
-
AD23
NA
dss_data4
0
IO
L
L
7
vdds
No
4
PU100/
LVCMOS
PD100
uart3_rx_irrx
2
I
gpio_74
4
IO
safe_mode
7
-
AD24
NA
dss_data5
0
IO
L
L
7
vdds
No
4
PU100/
LVCMOS
PD100
uart3_tx_irtx
2
O
gpio_75
4
IO
safe_mode
7
-
AC26
NA
dss_data10
0
IO
L
L
7
vdds
NA
4
PU100/
LVCMOS
PD100
gpio_80
4
IO
safe_mode
7
-
AD26
NA
dss_data11
0
IO
L
L
7
vdds
NA
4
PU100/
LVCMOS
PD100
gpio_81
4
IO
safe_mode
7
-
AA25
NA
dss_data12
0
IO
L
L
7
vdds
NA
4
PU100/
LVCMOS
PD100
gpio_82
4
IO
safe_mode
7
-
Y25
NA
dss_data13
0
IO
L
L
7
vdds
NA
4
PU100/
LVCMOS
PD100
gpio_83
4
IO
safe_mode
7
-
AA26
NA
dss_data14
0
IO
L
L
7
vdds
NA
4
PU100/
LVCMOS
PD100
gpio_84
4
IO
safe_mode
7
-
AB26
NA
dss_data15
0
IO
L
L
7
vdds
NA
4
PU100/
LVCMOS
PD100
gpio_85
4
IO
safe_mode
7
-
F25
NA
dss_data20
0
O
H
H
7
vdds
Yes
4
PU100/
LVCMOS
PD100
48
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