ICS932S801AFLF datasheet(11/20 Pages) ETC2

Part #	ICS932S801AFLF

Description	K8 Clock Chip for Serverworks GC-HT 2-Way Servers

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Manufacturer	ETC2 [List of Unclassifed Manufacturers]

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11

ICS932S801

0959C—03/13/06

SMBus Table: Frequency Select and Spread Control Register

Pin #

Name

Control Function

Type0

1PWD

Bit 7

FS Source

Latched Input or SMBus

Frequency Select

RW

Latched

Inputs

SMBus

0

Bit 6

CPU SS_EN

RW

OFF

ON

0

Bit 5

SRC SS_EN

RW

OFF

ON

0

Bit 4

Reserved

RW

Reserved

0

Bit 3

FS3

Freq Select Bit 3

RW

0

Bit 2

FS2

Freq Select Bit 2

RW

Latched

Bit 1

FS1

Freq Select Bit 1

RW

Latched

Bit 0

FS0

Freq Select Bit 0

RW

Latched

SMBus Table: Output Control Register

Pin #

Name

Control Function

Type0

1PWD

Bit 7

PCICLK3

Output Enable

RW

Disable (Low)

Enable

1

Bit 6

PCICLK2

Output Enable

RW

Disable (Low)

Enable

1

Bit 5

PCICLK1

Output Enable

RW

Disable (Low)

Enable

1

Bit 4

PCICLK0

Output Enable

RW

Disable (Low)

Enable

1

Bit 3

HTTCLK3

Output Enable

RW

Disable (Low)

Enable

1

Bit 2

HTTCLK2

Output Enable

RW

Disable (Low)

Enable

1

Bit 1

HTTCLK1

Output Enable

RW

Disable (Low)

Enable

1

Bit 0

HTTCLK0

Output Enable

RW

Disable (Low)

Enable

1

SMBus Table: Output Control Register

Pin #

Name

Control Function

Type0

1PWD

Bit 7

48MHz_1

Output Enable

RW

Disable (Low)

Enable

1

Bit 6

48MHz_0

Output Enable

RW

Disable (Low)

Enable

1

Bit 5

REF1

Output Enable

RW

Disable (Low)

Enable

1

Bit 4

REF0

Output Enable

RW

Disable (Low)

Enable

1

Bit 3

CPUCLK8(3)

RW

Disable

Enable

1

Bit 2

CPUCLK8(2)

RW

Disable

Enable

1

Bit 1

CPUCLK8(1)

RW

Disable

Enable

1

Bit 0

CPUCLK8(0)

RW

Disable

Enable

1

Output Enable

When Disabled

CPUCLKT = 0

CPUCLKC = 1

-

Byte 1

Spread Enable for CPU

and SRC PLLs. Setting

SPREAD_EN to '1',

forces Spread ON for

both PLLs.

Byte 0

-

Byte 2

See Functionality Table on

Page 1

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