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5M240ZT100C4N Datasheet(PDF) 10 Page - Altera Corporation |
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5M240ZT100C4N Datasheet(HTML) 10 Page - Altera Corporation |
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10 / 30 page  3–10 Chapter 3: DC and Switching Characteristics for MAX V Devices Power Consumption MAX V Device Handbook May 2011 Altera Corporation Power Consumption You can use the Altera® PowerPlay Early Power Estimator and PowerPlay Power Analyzer to estimate the device power. f For more information about these power analysis tools, refer to the PowerPlay Early Power Estimator for Altera CPLDs User Guide and the PowerPlay Power Analysis chapter in volume 3 of the Quartus II Handbook. Timing Model and Specifications MAX V devices timing can be analyzed with the Altera Quartus® II software, a variety of industry-standard EDA simulators and timing analyzers, or with the timing model shown in Figure 3–2. MAX V devices have predictable internal delays that allow you to determine the worst-case timing of any design. The software provides timing simulation, point-to-point delay prediction, and detailed timing analysis for device-wide performance evaluation. You can derive the timing characteristics of any signal path from the timing model and parameters of a particular device. You can calculate external timing parameters, which represent pin-to-pin timing delays, as the sum of the internal parameters. f For more information, refer to AN629: Understanding Timing in Altera CPLDs. Figure 3–2. Timing Model for MAX V Devices I/O Pin I/O Input Delay t IN INPUT Global Input Delay t C4 t R4 Output Delay t OD t XZ t ZX t GLOB Logic Element I/O Pin t FASTIO Output Routing Delay User Flash Memory From Adjacent LE To Adjacent LE Input Routing Delay t DL t LUT t C LUT Delay Register Control Delay Register Delays t CO t SU t H t PRE t CLR Data-In/LUT Chain Data-Out t IODR Output and Output Enable Data Delay t IOE t COMB Combinational Path Delay |
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