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DS87C550-FNL Datasheet(PDF) 10 Page - Dallas Semiconductor |
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DS87C550-FNL Datasheet(HTML) 10 Page - Dallas Semiconductor |
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10 / 50 page  DS87C550 10 of 50 MEMORY RESOURCES As is convention within the 8051 architecture, the DS87C550 uses three memory areas. The total memory configuration of the DS87C550 is 8 kbytes of EPROM, 1 kbyte of data SRAM and 256 bytes of scratchpad or direct RAM. The 1 kbyte of data space SRAM is read/write accessible and is memory mapped. This on-chip SRAM is reached by the MOVX instruction. It is not used for executable memory. The scratchpad area is 256 bytes of register mapped RAM and is identical to the RAM found on the 80C52. There is no conflict or overlap among the 256 bytes and the 1k as they use different addressing modes and separate instructions. OPERATIONAL CONSIDERATION The erasure window of the windowed CLCC package should be covered without regard to the programmed/unprogrammed state of the EPROM. Otherwise, the device may not meet the AC and DC parameters listed in the datasheet. PROGRAM MEMORY On-chip ROM begins at address 0000h and is contiguous through 1FFFh (8k). Exceeding the maximum address of on-chip ROM will cause the DS87C550 to access off-chip memory. However, the maximum on-chip decoded address is selectable by software using the ROMSIZE feature. Software can cause the DS87C550 to behave like a device with less on-chip memory. This is beneficial when overlapping external memory, such as Flash, is used. With the ROMSIZE feature the maximum on-chip memory size is dynamically variable. Thus a portion of on-chip memory can be removed from the memory map to access off-chip memory, then restored to access on-chip memory. In fact, all of the on-chip memory can be removed from the memory map, allowing the full 64k memory space to be addressed as off-chip memory. ROM addresses that are larger than the selected maximum are automatically fetched from outside the part via Ports 0 & 2. A depiction of the ROM memory map is shown in Figure 2. The ROMSIZE register is used to select the maximum on-chip decoded address for ROM. Bits RMS2, RMS1, RMS0 (ROMSIZE2:0) have the following effect. Maximum on-chip RMS2 RMS1 RMS0 ROM Address 0 0 0 0k 0 0 1 1k (0h - 03FFh) 0 1 0 2k (0h - 07FFh) 0 1 1 4k (0h - 0FFFh) 1 0 0 8k (0h – 1FFFh) default 1 0 1 invalid - reserved 1 1 0 invalid - reserved 1 1 1 invalid - reserved The reset default condition is a maximum on-chip ROM address of 8 kbytes. Thus no action is required if this feature is not used. Therefore when accessing external program memory, the first 8 kbytes would be inaccessible. To select a smaller effective ROM size, software must alter bits RMS2-RMS0. Altering these bits requires a Timed Access procedure as explained below. The ROMSIZE register should be manipulated from a safe area in the program memory map. This is a program memory address that will not be affected by the change. For example, do not select a maximum ROM size of 4k from an internal ROM address of 5k. This would cause the current address to switch from internal to external and potentially cause invalid operation. Similarly, do not instantly switch from external to internal memory. |
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