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DS80CH11 Datasheet(PDF) 19 Page - Dallas Semiconductor |
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DS80CH11 Datasheet(HTML) 19 Page - Dallas Semiconductor |
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19 / 88 page  DS80CH11 011200 19/88 3.0 CORE MICROCONTROLLER 3.1 CORE MICRO OVERVIEW The SEM incorporates the Dallas High Speed Micro core which is a fully static CMOS 8051 compatible microcontroller with a new internal architecture designed for high performance. The higher speed operation of the microcontroller core comes not just from increasing the clock frequency, but from a newer, more efficient design of the internal architecture. The major features of the High Speed Micro Core include: • 4 clocks/machine cycle (8032 = 12) • Wasted cycles removed • Runs DC to 25 Mhz clock rates @ 5V • Single–cycle instruction in 160 ns • Uses less power for equivalent work • Dual data pointer • Optional variable length MOVX to access fast/slow RAM /peripherals 3.2 INSTRUCTION SET SUMMARY All instructions in the SEM perform the same functions as their 80C32 counterparts. Their affect on bits, flags, and other status functions are identical. However, the timing of each instruction is different. This applies both in absolute and relative number of clocks. For absolute timing of real–time events, the timing of software loops will need to be calculated using the table below. However, counter/timers default to run at the older 12 clocks per increment. Therefore, while soft- ware runs at higher speed, timer–based events need no modification to operate as before. Timers can be set to run at 4 clocks per increment cycle to take advantage of higher speed operation. The relative time of two instructions might be different in the new architecture than it was previously. For exam- ple, in the original architecture, the “MOVX A, @ DPTR” instruction and the “MOV direct, direct” instruction used two machine cycles or 24 oscillator cycles. Therefore, they required the same amount of time. In the GEM, the MOVX instruction can be done in two machine cycles or 8 oscillator cycles but the “MOV direct, direct” uses three machine cycles or 12 oscillator cycles. While both are faster than their original counterparts, they now have different execution times from each other. This is because in most cases, the SEM uses one cycle for each byte. The timing of each instruction should be examined for familiarity with the changes. Note that a machine cycle now requires just four clocks, and pro- vides one ALE pulse per cycle. Many instructions require only one cycle, but some require five. In the orig- inal architecture, all were one or two cycles except for MUL and DIV. INSTRUCTION SET SUMMARY Table 3–1 Legends: A – Accumulator Rn – Register R7–R0 direct – Internal Register address @Ri – Internal Register pointed–to by R0 or R1 (except MOVX) rel – 2’s complement offset byte bit – direct bit–address #data – 8–bit constant #data 16 – 16–bit constant addr 16 – 16–bit destination address addr 11 – 11–bit destination address |
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