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DS21Q42TN Datasheet(PDF) 3 Page - Dallas Semiconductor |
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DS21Q42TN Datasheet(HTML) 3 Page - Dallas Semiconductor |
3 / 119 page DS21Q42 3 of 119 Functional Description The receive side framer locates D4 (SLC–96) or ESF multiframe boundaries as well as detects incoming alarms including, carrier loss, loss of synchronization, blue (AIS) and yellow alarms. If needed, the receive side elastic store can be enabled in order to absorb the phase and frequency differences between the recovered T1 data stream and an asynchronous backplane clock which is provided at the RSYSCLK input. The clock applied at the RSYSCLK input can be either a 2.048 MHz clock or a 1.544 MHz clock. The RSYSCLK can be a burst clock with speeds up to 8.192 MHz. The transmit side of the DS21Q42 is totally independent from the receive side in both the clock requirements and characteristics. Data off of a backplane can be passed through a transmit side elastic store if necessary. The transmit formatter will provide the necessary frame/multiframe data overhead for T1 transmission. Reader’s Note: This data sheet assumes a particular nomenclature of the T1 operating environment. In each 125 us frame, there are 24 eight–bit channels plus a framing bit. It is assumed that the framing bit is sent first followed by channel 1. Each channel is made up of eight bits which are numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is the LSB and is transmitted last. Throughout this data sheet, the following abbreviations will be used: D4 Superframe (12 frames per multiframe) Multiframe Structure SLC–96 Subscriber Loop Carrier – 96 Channels (SLC–96 is an AT&T registered trademark) ESF Extended Superframe (24 frames per multiframe) Multiframe Structure B8ZS Bipolar with 8 Zero Substitution CRC Cyclical Redundancy Check Ft Terminal Framing Pattern in D4 Fs Signaling Framing Pattern in D4 FPS Framing Pattern in ESF MF Multiframe BOC Bit Oriented Code HDLC High Level Data Link Control FDL Facility Data Link |
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