DS21Q43A datasheet(2/60 Pages) DALLAS

Part #	DS21Q43A

Description	Quad E1 Framer

Download	60 Pages

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Manufacturer	DALLAS [Dallas Semiconductor]

Direct Link	https://www.maximintegrated.com/en.html

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DS21Q43A

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1.0 INTRODUCTION

The DS21Q43A Quad E1 Framer is made up of five main parts: framer #0, framer #1, framer #2, framer

#3, and the control port which is shared by all four framers. See the Block Diagram in Figure 1-1. Each

of the four framers within the DS21Q43A maintains the same register structure that appeared in the

DS2143. The two framer-select inputs (FS0 and FS1) are used to determine which framer within the

DS21Q43A is being accessed. In this manner, software written for the DS2143 can also be used in the

DS21Q43A with only slight modifications. Several new features have been added to the framers in the

DS21Q43A over the DS2143.

ADDED FEATURE

SECTION

Non-multiplexed parallel control port operation

2 and 13

Transmit side elastic store

10

Expanded access to Sa and Si bits

6

Control signals RFSYNC, RMSYNC, and TFSYNC

1

FAS word error counting

5

Code violation counting

5

Automatic AIS generation upon loss of frame sync

3

Automatic remote alarm generation

3

Per-channel signaling insertion

9 and 11

Per-channel loopback from RSER to TSER

8 and 11

Option to update error counters every 62.5 ms

5

CRC4 resync criteria met status bit

4

Elastic store reset

10

Hardware 3-state control

1

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