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DS21FT40 Datasheet(PDF) 53 Page - Dallas Semiconductor |
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DS21FT40 Datasheet(HTML) 53 Page - Dallas Semiconductor |
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53 / 87 page  DS21FT40 53 of 87 TAF: TRANSMIT ALIGN FRAME REGISTER (Address=20 Hex) (MSB) (LSB) Si 00 110 11 [Must be programmed with the 7 bit FAS word; the DS21FT40 does not automatically set these bits] SYMBOLS POSITION NAME AND DESCRIPTION Si TAF.7 International Bit. 0 TAF.6 Frame Alignment Signal Bit. 0 TAF.5 Frame Alignment Signal Bit. 1 TAF.4 Frame Alignment Signal Bit. 1 TAF.3 Frame Alignment Signal Bit. 0 TAF.2 Frame Alignment Signal Bit. 1 TAF.1 Frame Alignment Signal Bit. 1 TAF.0 Frame Alignment Signal Bit. TNAF: TRANSMIT NON–ALIGN FRAME REGISTER (Address=21 Hex) (MSB) (LSB) Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8 [Bit 2 must be programmed to one; the DS21FT40 does not automatically set this bit] SYMBOLS POSITION NAME AND DESCRIPTION Si TNAF.7 International Bit. 1 TNAF.6 Frame Non–Alignment Signal Bit. A TNAF.5 Remote Alarm (used to transmit the alarm). Sa4 TNAF.4 Additional Bit 4. Sa5 TNAF.3 Additional Bit 5. Sa6 TNAF.2 Additional Bit 6. Sa7 TNAF.1 Additional Bit 7. Sa8 TNAF.0 Additional Bit 8. 13.2 INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME On the receive side, there is a set of eight registers (RSiAF, RSiNAF, RRA, RSa4 to RSa8) that report the Si and Sa bits as they are received. These registers are updated with the setting of the Receive CRC4 Multiframe bit in Status Register 2 (SR2.1). The host can use the SR2.1 bit to know when to read these registers. The user has 2 ms to retrieve the data before it is lost. The MSB of each register is the first received. Please see the register descriptions below and the Transmit Data Flow diagram in Section 16 for more details. On the transmit side, there is also a set of eight registers (TSiAF, TSiNAF, TRA, TSa4 to TSa8) that via the Transmit Sa Bit Control Register (TSaCR), can be programmed to insert both Si and Sa data. Data is sampled from these registers with the setting of the Transmit Multiframe bit in Status Register 2 (SR2.5). The host can use the SR2.5 bit to know when to update these registers. It has 2 ms to update the data or else the old data will be retransmitted. The MSB of each register is the first bit transmitted. Please see the register descriptions below and the Transmit Data Flow diagram in Section 16 for more details. |
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