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DS1869-50 Datasheet(PDF) 4 Page - Dallas Semiconductor |
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DS1869-50 Datasheet(HTML) 4 Page - Dallas Semiconductor |
4 / 8 page DS1869 4 of 8 DS1869 DUAL PORT CONFIGURATION (TYPICAL EXAMPLE) Figure 2B The DS1869 is provided with two supply inputs -V and +V. The maximum voltage difference between the two supply inputs is +8.0 volts. The minimum voltage difference is +2.7 volts. All input levels are referenced to the negative supply input, -V. The voltage applied to any Dallastat terminal must not exceed the negative supply voltage (-V ) by -0.5 or the positive supply voltage (+V) by +0.5 volts. The minimum logic high level must be +2.4 volts with reference to the -V supply voltage input for +V=5V. A logic low level with reference to the -V supply voltage has a maximum value of +0.8 volts. Dallastats exhibit a typical wiper resistance of 400 ohms with a maximum wiper resistance of 1000 ohms. The maximum wiper current allowed through the Dallastat is specified at 1 milliamps (see DC Electrical Characteristics). NONVOLATILE WIPER SETTINGS Dallastats maintain the position of the wiper in the absence of power. This feature is provided through the use of EEPROM type memory cell arrays. During normal operation the position of the wiper is determined by the input multiplexer. Periodically, the multiplexer will update the EEPROM memory cells. The manner in which an update occurs has been optimized for reliability, durability, and performance. Additionally, the update operation is totally transparent to the user. When power is applied to the Dallastat, the wiper setting will be the last recorded in the EEPROM memory cells. If the Dallastat setting is changed after power is applied, the new value will be stored after a delay of 2 seconds. The initial storage of a new value after power-up occurs when the first change is made, regardless of when this change is made. After the initial change on power-up all subsequent changes of the wiper position will be recorded only if the 4 th LSB (out of a 6-bit total for 64 positions) is being changed. Thus any change greater than 12.5% of the total resistance range will trigger one EEPROM write cycle. Changes or storage to the EEPROM memory cells must allow for a 2-second delay to guarantee that updates will occur. The EEPROM memory cells are specified to accept greater that 50,000 writes before a wear-out condition. If the EEPROM memory cells do reach a wear-out condition, the Dallastat will still function properly while power is applied. However, on power-up the device’s wiper position will be that of the position last recorded before memory cell wear-out. |
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