Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

DS1803 Datasheet(PDF) 3 Page - Dallas Semiconductor

Part No. DS1803
Description  Addressable Dual Digital Potentiometer
Download  11 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS1803 Datasheet(HTML) 3 Page - Dallas Semiconductor

  DS1803 Datasheet HTML 1Page - Dallas Semiconductor DS1803 Datasheet HTML 2Page - Dallas Semiconductor DS1803 Datasheet HTML 3Page - Dallas Semiconductor DS1803 Datasheet HTML 4Page - Dallas Semiconductor DS1803 Datasheet HTML 5Page - Dallas Semiconductor DS1803 Datasheet HTML 6Page - Dallas Semiconductor DS1803 Datasheet HTML 7Page - Dallas Semiconductor DS1803 Datasheet HTML 8Page - Dallas Semiconductor DS1803 Datasheet HTML 9Page - Dallas Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 3 / 11 page
background image
DS1803
3 of 11
Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is
HIGH, defines a START condition.
Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is
HIGH, defines the STOP condition.
Data valid: The state of the data line represents valid data when, after a START condition, the data line
is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed
during the LOW period of the clock signal. There is one clock pulse per bit of data. Figure 2 details how
data transfer is accomplished on the 2-wire bus. Depending upon the state of the R/ W * bit, two types of
data transfer are possible.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between START and STOP conditions is not limited, and is determined
by the master device. The information is transferred byte-wise and each receiver acknowledges with a
ninth bit.
Within the bus specifications a regular mode (100 kHz clock rate) and a fast mode (400 kHz clock rate)
are defined. The DS1803 works in both modes.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the
reception of each byte. The master device must generate an extra clock pulse which is associated with this
acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into account. A master must signal an end of data to the slave
by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the master to generate the STOP condition.
1. Data transfer from a master transmitter to a slave receiver: The first byte transmitted by the
master is the control byte (slave address). Next follows a number of data bytes. The slave returns an
acknowledge bit after each received byte.
2. Data transfer from a slave transmitter to a master receiver: The first byte (the slave address) is
transmitted by the master. The slave then returns an acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received
bytes other than the last byte. At the end of the last received byte, a ‘not acknowledge’is returned.
The master device generates all of the serial clock pulses and the START and STOP conditions. A
transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START
condition is also the beginning of the next serial transfer, the bus will not be released.
The DS1803 may operate in the following two modes:
1. Slave receiver mode: Serial data and clock are received through SDA and SCL. After each byte is
received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the
beginning and end of a serial transfer. Address recognition is performed by hardware after reception
of the slave address and direction bit.


Html Pages

1  2  3  4  5  6  7  8  9  10  11 


Datasheet Download

Go To PDF Page

Related Electronics Part Number

Part No.DescriptionHtml ViewManufacturer
X9221 Dual E2POT™ Nonvolatile Digital Potentiometer 1  2  3  4  5  More Xicor Inc.
DS3908 Dual 64-Position Nonvolatile Digital Potentiometer with Buffered Outputs 1  2  3  4  5  More Maxim Integrated Products
AD5243 Dual 256-Position I2C Compatible Digital Potentiometer 1  2  3  4  5  More Analog Devices
AD5162 Dual 256-Position SPI Digital Potentiometer 1  2  3  4  5  More Analog Devices
AD5222 Increment/Decrement Dual Digital Potentiometer 1  2  3  4  5  More Analog Devices
DS1868 Dual Digital Potentiometer Chip 1  2  3  4  5  More Dallas Semiconductor
DS1881 Dual NV Audio Taper Digital Potentiometer 1  2  3  4  5  More Maxim Integrated Products
DS1805 Addressable Digital Potentiometer 1  2  3  4  5  More Maxim Integrated Products
AD5232 8-Bit Dual Nonvolatile Memory Digital Potentiometer 1  2  3  4  5  More Analog Devices

Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn