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DS1708T Datasheet(PDF) 1 Page - Dallas Semiconductor |
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DS1708T Datasheet(HTML) 1 Page - Dallas Semiconductor |
1 / 9 page ECopyright 1995 by Dallas Semiconductor Corporation. All Rights Reserved. For important information regarding patents and other intellectual property rights, please refer to Dallas Semiconductor data books. DS1707/DS1708 3.3 and 5.0 Volt MicroMonitor DS1707/DS1708 010996 1/9 FEATURES • Holds microprocessor in check during power tran- sients • Automatically restarts microprocessor after power failure • Monitors pushbutton for external override • Accurate 5%, 10% or 20% resets for 3.3 systems and 5% or 10% resets for 5.0 volt systems • Eliminates the need for discrete components • 20% tolerance compatible with 3.0 volt systems • Pin compatible with the MAXIM MAX707/MAX708 in 8–pin DIP and 8–pin SOIC packages • 8–pin DIP, 8–pin SOIC and 8–pin µ–SOP packages available • Industrial temperature range –40°C to +85°C PIN ASSIGNMENT RST RST NC NMI 1 2 3 4 PBRST VCC GND IN 8 7 6 5 8 7 6 5 1 2 3 4 PBRST VCC GND IN RST RST NC NMI 8–PIN DIP (300 MIL) 8–PIN SOIC (150 MIL) 1 2 3 4 8 7 6 5 PBRST VCC GND IN RST RST NC NMI 8–PIN µ–SOP (118 MIL) See Mech. Drawings Section DS1707 and DS1708_/R/S/T PIN DESCRIPTION PBRST – Pushbutton Reset Input VCC – Power Supply GND – Ground IN – Input NMI – Non–maskable Interrupt NC – No Connect RST – Active Low Reset Output RST – Active High Reset Output DESCRIPTION The DS1707/DS1708 3.3 or 5.0 Volt MicroMonitor moni- tors three vital conditions for a microprocessor: power supply, voltage sense, and external override. A preci- sion temperature–compensated reference and comparator circuit monitors the status of VCC at the device and at an upstream point for maximum protec- tion. When the sense input detects an out–of–tolerance condition a non–maskable interrupt is generated. As the voltage at the device degrades an internal power fail signal is generated which forces the reset to an active state. When VCC returns to an in–tolerance condition, the reset signal is kept in the active state for a minimum of 130 ms to allow the power supply and processor to stabilize. |
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