24C04A, 24C08A, 24C16A

© 2009 Fremont Micro Devices Inc.

DS3001M-page3

PIN DESCRIPTIONS

(A) SERIAL CLOCK (SCL)

The rising edge of this SCL input is to latch data into the EEPROM device while the falling edge of this clock is to

clock data out of the EEPROM device.

(B) DEVICE / CHIP SELECT ADDRESSES (A2, A1, A0)

These are the chip select input signals for the serial EEPROM devices. Typically, these signals are hardwired to

FT24C08A has both A0 and A1 pins as no-connect. For FT24C16A, all device address pins (A0-A2) are no-

connect.

(C) SERIAL DATA LINE (SDA)

SDA data line is a bi-directional signal for the serial devices. It is an open drain output signal and can be wired-

OR with other open-drain output devices.

(D) WRITE PROTECT (WP)

The FT24C04A/08A/16A devices have a WP pin to protect the whole EEPROM array from programming.

level.

Table A

Device

Chip Select/Device

Address Pins Used

No-Connect Pins

Max number of similar

devices on the same bus

FT24C04A

A2, A1

A0

4

FT24C08A

A2,

A1, A0

2

FT24C16A

(None)

A2, A1, A0

1

MEMORY ORGANIZATION

The FT24C04A/08A/16A devices have 32/64/128 pages respectively. Since each page has 16 bytes, random word

addressing to FT24C04A/08A/16A will require 9/10/11 bits data word addresses respectively.

DEVICE OPERATION

(A) SERIAL CLOCK AND DATA TRANSITIONS

The SDA pin is typically pulled to high by an external resistor. Data is allowed to change only when Serial clock

(B) START CONDITION

With SCL

must begin with a START condition.