DS1244/DS1244P

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to the first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are executed using the

CE

phantom clock. Therefore, any address to the memory in the socket is acceptable. However, the write

cycles generated to gain access to the phantom clock are also writing data to a location in the mated

RAM. The preferred way to manage this requirement is to set aside just one address location in RAM as a

phantom clock scratch pad. When the first write cycle is executed, it is compared to bit 0 of the 64-bit

comparison register. If a match is found, the pointer increments to the next location of the comparison

register and awaits the next write cycle. If a match is not found, the pointer does not advance and all

subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition, the

present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues for

a total of 64 write cycles as described above until all the bits in the comparison register have been

matched (Figure 1). With a correct match for 64 bits, the phantom clock is enabled and data transfer to or

from the timekeeping registers can proceed. The next 64 cycles will cause the phantom clock to either

recognition sequence or data transfer sequence to the phantom clock.

PHANTOM CLOCK REGISTER INFORMATION

The phantom clock information is contained in eight registers of 8 bits, each of which is sequentially

accessed 1 bit at a time after the 64-bit pattern recognition sequence has been completed. When updating

the phantom clock registers, each register must be handled in groups of 8 bits. Writing and reading

individual bits within a register could produce erroneous results. These read/write registers are defined in

Figure 2.

Data contained in the phantom clock register is in binary coded decimal (BCD) format. Reading and

writing the registers is always accomplished by stepping through all eight registers, starting with bit 0 of

register 0 and ending with bit 7 of register 7.