CYStech Electronics Corp.

Spec. No. : C705Q8

Issued Date : 2007.08.22

Revised Date :

Page No. : 5/12

CTK24BC01-16Q8

CYStek Product Specification

AC Characteristics(Cont.)

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

Stop Setup Time

4.7

0.6

-

-

μs

Data out Hold Time

100

50

-

-

ns

Write Cycle Time

-

-

5

5

ms

5.0V, 25℃, Byte Mode

Endurance

(Note 1)

1M

1M

-

-

Write

Cycles

Note: 1. This parameter is characterized and not 100% tested.

Device Operation

Clock and Data Transitions: Transitions on the SDA pin should only occur when SCL is low(refer to the

Data Validity timing diagram in Figure 3). If the SDA pin changes when SCL is high, then the transition

will be interpreted as a START or STOP condition.

START Condition: A START condition occurs when the SDA transitions from high to low when SCL is

high. The START signal is usually used to initiate a command(refer to the START and STOP definition

timing diagram in Fig 4)

STOP Condition: A STOP condition occurs when the SDA transitions from low to high when SCL is high.

(refer to the START and STOP definition timing diagram in Fig 4) The STOP command will put the device

into standby mode after no acknowledgement is issued during the read sequence.

Acknowledge: An acknowledgement is sent by pulling the SDA low to confirm that a word has been

successfully received. All addresses and data words are serially transmitted to and from the EEPROM in

Standby Mode: Standby mode is entered when the chip is initially powered-on or after a STOP command

has been issued and any internal operations have been completed.

Memory Reset: In the event of unexpected power or connection loss, a START condition can be issued to

restart the input command sequence. If the device is currently in write cycle mode, this command will be

ignored.