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occurs and both ABE and AE are set. The ABE and AE bits are cleared during the power-up transition,

however an alarm generated during power-up will set AF. Therefore the AF bit can be read after system

power-up to determine if an alarm was generated during the power-up sequence. Figure 4 illustrates alarm

timing during the battery back-up mode and power-up states.

BACK-UP MODE ALARM WAVEFORMS Figure 4

USING THE WATCHDOG TIMER

The watchdog timer can be used to detect an out-of-control processor. The user programs the watchdog

timer by setting the desired amount of time-out into the 8-bit Watchdog Register (Address 7FF7h). The

five Watchdog Register bits BMB4-BMB0 store a binary multiplier and the two lower order bits RB1-

RB0 select the resolution, where 00=1/16 second, 01=1/4 second, 10=1 second, and 11=4 seconds. The

watchdog time-out value is then determined by the multiplication of the 5-bit multiplier value with the 2-

bit resolution value. (For example: writing 00001110 in the Watchdog Register = 3 X 1 second or 3

seconds.) If the processor does not reset the timer within the specified period, the Watchdog Flag (WF) is

set and a processor interrupt is generated and stays active until either the Watchdog Flag (WF) is read or

the Watchdog Register (7FF7) is read or written.

The most significant bit of the Watchdog Register is the Watchdog Steering Bit (WDS). When set to a 0,

40 ms to 200 ms. The Watchdog Register (7FF7) and the FT bit will reset to a 0 at the end of a watchdog

time-out when the WDS bit is set to a 1.

The watchdog timer resets when the processor performs a read or write of the Watchdog Register. The

time-out period then starts over. The watchdog timer is disabled by writing a value of 00h to the

Watchdog Register. The watchdog function is automatically disabled upon power-up and the Watchdog

function is activated, the watchdog function prevails and the frequency test function is denied.