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DS9034PCX Datasheet(PDF) 3 Page - Dallas Semiconductor |
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DS9034PCX Datasheet(HTML) 3 Page - Dallas Semiconductor |
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3 / 19 page  DS1557 3 of 19 DS1557 OPERATING MODES Table 1 VCC CE OE WE DQ0-DQ7 MODE POWER VIH X X HIGH-Z DESELECT STANDBY VIL XVIL DIN WRITE ACTIVE VIL VIL VIH DOUT READ ACTIVE VCC > VPF VIL VIH VIH HIGH-Z READ ACTIVE VSO < VCC <VPF X X X HIGH-Z DESELECT CMOS STANDBY VCC < VSO X X X HIGH-Z DATA RETENTION BATTERY CURRENT DATA READ MODE The DS1557 is in the read mode whenever CE (chip enable) is low and WE (write enable) is high. The device architecture allows ripple-through access to any valid address location. Valid data will be available at the DQ pins within tAA after the last address input is stable, providing that CE and OE access times are satisfied. If CE or OE access times are not met, valid data will be available at the latter of chip enable access (tCEA) or at output enable access time (tOEA). The state of the data input/output pins (DQ) is controlled by CE and OE . If the outputs are activated before tAA, the data lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and OE remain valid, output data will remain valid for output data hold time (tOH ) but will then go indeterminate until the next address access. DATA WRITE MODE The DS1557 is in the write mode whenever WE and CE are in their active state. The start of a write is referenced to the latter occurring transition of WE or CE . The addresses must be held valid throughout the cycle. CE and WE must return inactive for a minimum of tWR prior to the initiation of a subsequent read or write cycle. Data in must be valid tDS prior to the end of the write and remain valid for tDH afterward. In a typical application, the OE signal will be high during a write cycle. However, OE can be active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low, the data bus can become active with read data defined by the address inputs. A low transition on WE will then disable the outputs tWEZ after WE goes active. DATA RETENTION MODE The 5-volt device is fully accessible and data can be written and read only when VCC is greater than VPF. However, when VCC is below the power-fail point VPF (point at which write protection occurs) the internal clock registers and SRAM are blocked from any access. When VCC falls below the battery switch point VSO (battery supply level), device power is switched from the VCC pin to the internal backup lithium battery. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal levels. The 3.3-volt device is fully accessible and data can be written and read only when VCC is greater than VPF. When VCC falls below VPF, access to the device is inhibited. If VPF is less than VBAT, the device power is switched from VCC to the internal backup lithium battery when VCC drops below VPF. If VPF is greater than VBAT, the device power is switched from VCC to the internal backup lithium battery when VCC drops below VBAT. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal levels. All control, data, and address signals must be powered down when VCC is powered down. |
Similar Part No. - DS9034PCX |
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Similar Description - DS9034PCX |
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