DS1481

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OPERATION

One wire communication is executed in “time slots”.

The DS1481 generates either a read/write bit “time slot”

or a reset on the I/O pin. The operation performed is

determined by the states of the D/CLK and RES pins as

follows:

TIME SLOT

D/CLK

RES

Read 0, Read 1,

Write 1

logic high

logic high (see

Figure 4)

Write 0

logic low

logic high (see

Figure 5)

1–wire Reset

logic high

logic low (see

Figure 6)

After D/CLK and RES have been set, the time slot

begins when ENI is driven to its active state. A falling

edge on ENI causes the DS1481 to save the state of

D/CLK and RES. If the time slot is a 1–wire reset the

DS1481 will issue a busy signal by driving O1/BSY1 low

and O2/BSY2 high. After 2

µs O2/BSY2 is driven low.

Both outputs will remain low until the communication on

the I/O line is finished. A busy signal for a bit time slot

differs from the reset busy signal only in that both

O1/BSY1 and O2/BSY2 are driven low immediately.

While the busy signal is asserted, the host processor is

free to perform other tasks (including running the print

spooler). When the time slot is complete, the DS1481

restores both O1/BSY1 and O2/BSY2 to the states of I1

and I2 (see Figure 1).

When the host detects that one or both of the busy sig-

nals has returned high, it must query the result of the

time slot. This is accomplished by driving D/CLK low. If

the result of the time slot was low (Read 0, Write 0 or

presence detect) the DS1481 drives both O1/BSY1 and

O2/BSY2 low (this state is held until ENI returns high).

Otherwise it propagates the states of I1 and I2.

After the host reads the result of the time slot it must

drive ENI to its inactive state (high). The DS1481 will

then set O1/BSY1 and O2/BSY2 to the states of I1

and I2.

1–WIRE TIMING GENERATION

(see Figure 4). The DS1481 waits a minimun of 60

µs

from the start of the time slot and de–asserts O1/BSY1

and O2/BSY2.

When a reset is requested, the DS1481 drives the I/O

pin low for at least 480

µs and then releases it. During a

normal reset the I/O pin immediately begins to return

high.

If a 1–wire device is present on the I/O line it pulls I/O low

after time T (15

µs ≤ T ≤ 60 µs) from the previous rising

edge. The 1–wire device(s) holds the I/O line low for 4T

and then releases it, allowing the I/O line to return high.

This is the presence detect pulse. The I/O line must

remain high (in its idle state) for at least 3T before the

1–wire device(s) is ready for further communication. To

insure this idle high time is satisfied, the DS1481 does

not release O1/BSY1 and O2/BSY2 for at least 960

µs

(measured from the 1st falling edge on the I/O pin).

If after 480

µs of low time the I/O line did not return high,

either the I/O line has been shorted to ground or there is

at least one 1–wire device connected to the I/O line

which is issuing an alarm interrupt (see Figure 6). In this

case the DS1481 waits for I/O to return high for an addi-

tional 3840

µs (64 * 60). If time expires the I/O line is

assumed to be shorted and the DS1481 releases

O1/BSY1 and O2/BSY2. If the I/O line returns high, the

DS1481 continues to monitor the presence detect por-

tion of the reset (as described above) as for the non–in-

terrupt case. Note that the 3T idle high time is still

required after the presence detect ends.

OVERDRIVE

The DS1481 also supports overdrive communication

with overdrive capable 1–wire devices. When the

DS1481 powers up it is in normal mode (i.e., OD = 0,

Figure 1). To toggle to overdrive mode the host sets

D/CLK and RES low and drives ENI low. The DS1481

toggles the OD bit to a logic high and returns the states

of I1 and I2 on O1/BSY1 and O2/BSY2. Overdrive

mode is cleared in the same way. When overdrive is

turned off (OD = 0). O1/BSY1 and O2/BSY2 are driven

low to report the state of the OD bit.