DS1384

4 of 17

For more information on crystal selection and crystal layout considerations, please consult Application

Note 58, “Crystal Considerations with Dallas Real Time Clocks.”

SQW - Square Wave (output): This pin can be programmed to output a 1024 Hz square wave signal.

When the signal is turned off, the pin is high Z.

PFO

ADDRESS DECODING

The DS1384 accommodates 17 address lines, which allows direct connection of up to 128k bytes of static

RAM. The lower 14 bytes of RAM, regardless of the density used, will always contain the timekeeping,

alarm, and watchdog registers. The 14 clock registers reside in the lower 14 RAM locations without

timekeeping chip actually contains 64 registers (14 RTC and 50 user RAM), the lower 64 bytes of any

attached memory resides within the DS1384. However, the RAM’s physical location is transparent to the

user and the memory map looks continuous from the first clock address to the upper most attached RAM

address.

OPERATION - READ CYCLE

unique address specified by the address inputs (A0-A16) defines which of the on-chip 64 RTC/RAM or

external SRAM locations is to be accessed. When the address value presented to the DS1384 is in the

range of 00000H through 0003FH, one of the 64 on-chip registers will be selected and valid data will be

OER

signal will remain inactive throughout the read cycle.

When the address value presented to the DS1384 is in the range of 00040H through 1FFFFH, an external

OPERATION - WRITE CYCLE

CE