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IS6667WV51216DBLL Datasheet(PDF) 8 Page - List of Unclassifed Manufacturers

Part # IS6667WV51216DBLL
Description  8Mb LOW VOLTAGE, ULTRA LOW POWER PSEUDO CMOS STATIC RAM
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Integrated Silicon Solution, Inc. — www.issi.com
Rev.  A
06/28/2011
IS66WV51216DALL
IS66/67WV51216DBLL
DATA VALID
PREVIOUS DATA VALID
tAA
tOHA
tOHA
tRC
DQ0-D15
ADDRESS
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = VIL, cS2 = WE = VIH, UB or LB = VIL)
READ CYCLE SWITCHING CHARACTERISTICS(1)(Over Operating Range)
                                   55 ns                                       70 ns 
  Symbol 
Parameter 
Min. 
Max. 
Min. 
Max. 
Unit
trc
Read Cycle Time
55
70
ns
tAA
Address Access Time
55
70
ns
toHA
Output Hold Time
10
10
ns
tAcS1/tAcS2
CS1/
CS2 Access Time
55
70
ns
tdoe
OE
Access Time
25
35
ns
tHzoe(2)
OE
to High-Z Output
20
25
ns
tLzoe(2)
OE
to Low-Z Output
5
5
ns
tHzcS1/tHzcS2(2) CS1/CS2 to High-Z Output
0
20
0
25
ns
tLzcS1/tLzcS2(2) CS1/CS2 to Low-Z Output
10
10
ns
tBA
LB
, UB Access Time
55
70
ns
tHzB
LB
, UB to High-Z Output
0
20
0
25
ns
tLzB
LB
, UB to Low-Z Output
0
0
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to
Vdd-0.2V/0.4V to Vdd-0.3V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±100 mV from steady-state voltage. Not 100% tested.


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