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DS1040Z-100 Datasheet(PDF) 5 Page - Dallas Semiconductor |
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DS1040Z-100 Datasheet(HTML) 5 Page - Dallas Semiconductor |
5 / 6 page DS1040 5 of 6 POWER-UP TIMING DIAGRAM Figure 3 TEST CIRCUIT Figure 4 TERMINOLOGY Period: The time elapsed between the leading edge of the first trigger pulse and the leading edge of the following trigger pulse. tWIH , WIL , WO (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the 1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading edge. |
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