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IRAUDAMP9 Datasheet(PDF) 11 Page - International Rectifier |
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IRAUDAMP9 Datasheet(HTML) 11 Page - International Rectifier |
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11 / 39 page  www.irf.com IRAUDAMP9 REV 1.0 Page 11 of 39 signal shifts the average value of this quadratic waveform (through gain relationship between R52 / R46 ratio) so that the duty varies according to the instantaneous value of the analog input signal. The IRS2092S input comparator processes the signal to create the required PWM signal. This PWM signal is internally level-shifted down to the negative supply rail where it is split into two signals, with opposite polarity and added dead time, for high-side and low-side MOSFET gate signals, respectively. The IRS2092S drives 2 pairs of IRFB4227 TO-220 MOSFETs in the power stage to provide the amplified PWM waveform. The amplified analog output is re-created by demodulating the amplified PWM. This is done by means of the LC low-pass filter (LPF) formed by L4 and C34, which filters out the switching carrier signal. Gate Driver Buffer Stage High power designs such as IRAUDAMP9 that use multiple mosfets in parallel connection to handle large amount of switching current often require far more than +/-1A drive current even for a brief moment due to mosfets’ gate drive requirement (high total gate charge, Qg). In order to facilitate this high drive current, a buffer stage is devised to source and sink this high gate charge. This stage consists of NPN-PNP BJT transistors in totem pole configuration. It serves as a high- speed buffer amplifier that receives input from IRS2092S HO / LO to drive the power mosfet stage through Rg (1A,1B,2A,2B) for low side mosfets Q4(A,B) and for high-side Q3 (A,B) mosfets. Theoretically, the switching time is reduced by such amount (hfe) as compared to that high-Qg design that uses the divided output current capacity of the driver IC. This buffering action is very necessary to speed-up the switching times of each mosfets in order not to exceed the OCP voltage monitor time. The IC commences drain-to-source voltage monitoring as soon as the HO / LO go to high state but after the leading edge blanking time. +B Czobel Rzobel -B Q3A Q4A Q3B Q4B Q1p Q2p Q1n Q2n Cvcc2 Cvcc1 VB Rg2A Rgs4A Rg2B Rgs4B Rg1A Rg1B Rgs3A Rgs3B Cbus filter HO LO RLoad Cout filter L out filter Vs GND -B Vout VCC Fig. 8 Simplified diagram for gate-buffering of 2 x IRFB4227 mosfets BJT buffer Low side BJT buffer Hi-side |
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