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DS1077Z-120 Datasheet(PDF) 17 Page - Dallas Semiconductor |
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DS1077Z-120 Datasheet(HTML) 17 Page - Dallas Semiconductor |
17 / 21 page DS1077 17 of 21 8) A fast mode device can be used in a standard mode system, but the requirement t SU :DAT>250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t R MAX + tSU :DAT = 1000ns + 250ns = 1250ns before the SCL line is released. 9) C B is the total capacitance of one bus line in pF. 10) OUT0 and OUT1 are operating at oscillator master frequency without divider. 11) Typical frequency shift due to aging is ±0.5%. Aging stressing includes Level 3 preconditioning with 1000 temperature cycles of -55°C to +125°C, 336hr max VCC biased +125°C bake. Level 3 preconditioning consists of a 24hr +125°C storage bake, 192hr moisture soak at +30°C/60% R.H., and three solder reflow passes. TIMING DIAGRAM SU:STO t t SP HD:STA t t SU:STA SU:DAT t tHIGH R t t LOW tHD:STA SCL START SDA STOP tBUF tF REPEATED START tHD:DAT ORDERING INFORMATION Example: DS1077Z-100 DS1077 Z = SO U = µSOP 133 = 133.333MHz 125 = 125.000MHz 120 = 120.000MHz 100 = 100.000MHz 66 = 66.666MHz |
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