Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF Download HTML

DS1077Z-125 Datasheet(PDF) 16 Page - Dallas Semiconductor

Part No. DS1077Z-125
Description  EconOscillator/Divider
Download  21 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS1077Z-125 Datasheet(HTML) 16 Page - Dallas Semiconductor

Back Button DS1077Z-125 Datasheet HTML 12Page - Dallas Semiconductor DS1077Z-125 Datasheet HTML 13Page - Dallas Semiconductor DS1077Z-125 Datasheet HTML 14Page - Dallas Semiconductor DS1077Z-125 Datasheet HTML 15Page - Dallas Semiconductor DS1077Z-125 Datasheet HTML 16Page - Dallas Semiconductor DS1077Z-125 Datasheet HTML 17Page - Dallas Semiconductor DS1077Z-125 Datasheet HTML 18Page - Dallas Semiconductor DS1077Z-125 Datasheet HTML 19Page - Dallas Semiconductor DS1077Z-125 Datasheet HTML 20Page - Dallas Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 16 / 21 page
background image
DS1077
16 of 21
AC ELECTRICAL CHARACTERISTICS: 2-WIRE INTERFACE
(-40
°C to +85°C; VCC= 5V±5%)
PARAMETER
SYMBOL
CONDITION
MIN
TYP MAX UNITS NOTES
Fast Mode
400
SCL Clock Frequency
f
SCL
Standard Mode
100
kHz
Fast Mode
1.3
Bus Free Time
Between a STOP
and START Condition
t
BUF
Standard Mode
4.7
µs
Fast Mode
0.6
Hold Time (Repeated)
START Condition
t
HD
:STA
Standard Mode
4.0
µs
6
Fast Mode
1.3
LOW Period of SCL
t
LOW
Standard Mode
4.7
µs
Fast Mode
0.6
HIGH Period of SCL
t
HIGH
Standard Mode
4.0
µs
Fast Mode
0.6
Set-Up Time for a
Repeated START
t
SU
:STA
Standard Mode
4.7
µs
Fast Mode
0
Data Hold Time
t
HD
:DAT
Standard Mode
0
0.9
µs
7,8
Fast Mode
100
Data Set-Up Time
t
SU
:DAT
Standard Mode
250
ns
Fast Mode
300
Rise Time of Both
SDA and SCL Signals
t
R
Standard Mode
20 + 0.1
C
B
1000
ns
9
Fast Mode
Fall Time of Both SDA
and SCL Signals
t
F
Standard Mode
20 + 0.1
C
B
300
ns
9
Fast Mode
0.6
Set-Up Time For STOP
t
SU
:STO
Standard Mode
4.0
µs
Capacitive Load for
Each Bus Line
C
B
400
pF
9
Input Capacitance
C
I
5pF
NONVOLATILE MEMORY CHARACTERISTICS
PARAMETER
SYMBOL CONDITION
MIN
TYP
MAX
UNITS NOTES
Writes
+85°C
10,000
NOTES:
1) All voltages are referenced to ground.
2) 8.13kHz is obtained from a -66MHz standard part.
3) PDN is a power-down signal applied to either CTRL0 or CTRL1 pins as appropriate.
4) Output voltage swings may be impaired at high frequencies combined with high output loading.
5) After this period, the first clock pulse is generated.
6) A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
IH
MIN
of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
7) The maximum t
HD
:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL
signal.


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21 


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn