DS1000-150 datasheet(2/5 Pages) DALLAS

Part #	DS1000-150

Description	5-Tap Silicon Delay Line

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Manufacturer	DALLAS [Dallas Semiconductor]

Direct Link	https://www.maximintegrated.com/en.html

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DS1000

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LOGIC DIAGRAM Figure 1

DS1000

PART NUMBER DELAY TABLE (all values in ns) Table 1

TAP 1TAP 2TAP 3

TAP 4

TAP 5

TOLERANCE

PART #

DS1000-

Nom

Init

Temp

Nom

Init

Temp

Nom

Init

Temp

Nom

Init

Temp

Nom

Init

Temp

-20

4

2

1

8

2

1122

1162

1

20

2

1

-25

5

2

1

10

2

1

15

2

1

20

2

1

25

2

1

-30

6

2

1

12

2

1

18

2

1

24

2

1

30

2

1

-35

7

2

1

14

2

1

21

2

1

28

2

1

35

2

1.1

-40

8

2

1

16

2

1

24

2

1

32

2

1

40

2

1.2

-45

9

2

1

18

2

1

27

2

1

36

2

1.1

45

2.3

1.4

-50

10

2

1

202

1302

1402

1.2

50

2.5

1.5

-60

12

2

1

242

1362

1.1

48

2.4

1.5

60

3

1.8

-75

15

2

1

302

145

2.3

1.4

603

1.8

75

3.8

2.3

-100

20

2

1

40

2

1.2

60

3

1.8

80

4

2.4

100

5

3

-125

25

2

1

50

2.5

1.5

75

3.8

2.3

100

5

3

125

6.3

3.8

-150

30

2

1

60

3

1.8

90

4.5

2.7

120

6

3.6

150

7.5

4.5

-175

35

2

1.1

70

3.5

2.1

105

5.3

3.2

140

7

4.2

175

8.8

5.3

-200

40

2

1.2

80

4

2.4

120

6

3.6

160

8

4.8

200

10

6

-250

50

2.5

1.5

100

5

3

150

7.5

4.5

200

10

6

250

12.5

7.5

-500

100

5

3

200

10

6

300

15

9

400

20

12

500

25

15

DC ELECTRICAL CHARACTERISTICS

(0°C to 70°C; VCC = 5.0V ± 5%)

PARAMETER

SYM

TEST

CONDITION

MIN

TYP

MAX

UNITS

NOTES

Supply Voltage

VCC

4.75

5.00

5.25

V

6

High Level Input

Voltage

VIH

2.2

VCC + 0.5

V

6

Low Level Input

Voltage

VIL

-0.5

0.8

V

6

Input Leakage

Current

II

0.0V

≤ V

I

≤ V

CC

-1.0

1.0

uA

Active Current

ICC

VCC=Max;

Period=Min.

35

75

mA

7, 9

High Level Output

Current

IOH

VCC=Min.

VOH=4

-1

mA

Low Level Output

Current

IOL

VCC=Min.

VOL=0.5

12

mA

AC ELECTRICAL CHARACTERISTICS

(TA = 25°C; VCC = 5V ± 5%)

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Input Pulse Width

tWI

40% of Tap 5 tPLH

ns

8

Input to Tap Delay

(leading edge)

tPLH

Table 1

ns

1, 2, 3, 4,

5, 10

Input to Tap Delay

(trailing edge)

tPHL

Table 1

ns

1, 2, 3, 4,

5, 10

Power-up Time

tPU

100

ms

Input Period

Period

4 (tWI)ns

8

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