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DS1005-60 Datasheet(PDF) 5 Page - Dallas Semiconductor

Part No. DS1005-60
Description  5-Tap Silicon Delay Line
Download  6 Pages
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Maker  DALLAS [Dallas Semiconductor]
Homepage  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS1005-60 Datasheet(HTML) 5 Page - Dallas Semiconductor

  DS1005-60 Datasheet HTML 1Page - Dallas Semiconductor DS1005-60 Datasheet HTML 2Page - Dallas Semiconductor DS1005-60 Datasheet HTML 3Page - Dallas Semiconductor DS1005-60 Datasheet HTML 4Page - Dallas Semiconductor DS1005-60 Datasheet HTML 5Page - Dallas Semiconductor DS1005-60 Datasheet HTML 6Page - Dallas Semiconductor  
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DS1005
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TEST SETUP DESCRIPTION
Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1005.
The input waveform is produced by a precision pulse generator under software control. Time delays are
measured by a time interval counter (20 ps resolution) connected between the input and each tap. Each
tap is selected and connected to the counter by a VHF switch control unit. All measurements are fully
automated, with each instrument controlled by a central computer over an IEEE 488 bus.
TEST CONDITIONS
INPUT:
Ambient Temperature
25
°C ±=3°C
Supply Voltage (VCC)
5.0V
±=0.1V
Input Pulse
High = 3.0V
±=0.1V
Low = 0.0V
±=0.1V
Source Impedance
50 ohm maximum
Rise and Fall Time
3.0 ns maximum
Pulse Width
500 ns
Period
1
µs
OUTPUT:
Each output is loaded with the equivalent of a 74F04 input gate. Delay is measured at the 1.5V level on
the rising and falling edge.
NOTE:
Above conditions are for test only and do not restrict the operation of the device under other data sheet
conditions.


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